Adjust VM apb address map for easier use

IP_wrappers/synopsys_VM_sensor_integration.v

@@ -31,7 +31,7 @@ module synopsys_VM_sensor_integration(
 //      - 23-17 RESERVED
 //      - 16    vm_local_reset
 //      - 15-8  vm_clk_div
-//      - 7-4   vm_sel_vin
+//      - 7-4   RESERVED
 //      - 3     vm_ready_reg_clr
 //      - 2     vm_run_continuous_reg
 //      - 1     vm_enable_reg
@@ -45,11 +45,11 @@ module synopsys_VM_sensor_integration(
 //      - 11-0  vm_data
 //
 // 0x08 - 31-25 RESERVED
-//      - 19-16 vm_tm_an
+//      - 19-16 
 //      - 15-9  RESERVED
-//      - 8     vm_sig_en
+//      - 8     
 //      - 7-1   RESERVED
-//      - 0     vm_cal
+//      - 0-3   vm_sel_vin
 //
 // 0x0C - 31-0  ID
 
@@ -191,7 +191,7 @@ end
 // reg 0 assignments in PCLK domain
 assign vm_clock_div = data0[15:8];
 assign vm_enable = data0[1];
-assign vm_sel_vin = data0[7:4];
+assign vm_sel_vin = data2[3:0];
 // vm Clock generation
 assign vm_clkg = PCLK & vm_enable;
 always @(posedge vm_clkg or negedge PRESETn) begin
@@ -253,9 +253,9 @@ always @(posedge vm_slow_clock or negedge PRESETn) begin
     if(~PRESETn) begin
         vm_run <= 1'b0;
     end else begin
-        if(~vm_ready_reg & vm_run_req)
+        if(~vm_ready & vm_run_req)
             vm_run <= 1'b1;
-        else if (vm_ready_reg & ~vm_run_req)
+        else if (vm_ready & ~vm_run_req)
             vm_run <= 1'b0;
     end
 end
@@ -267,9 +267,6 @@ end
 assign vm_local_reset = vm_data0[16];
 assign vm_pd = vm_data0[1];
 
-assign vm_tm_an = vm_data2[19:16];
-assign vm_sig_en = vm_data2[8];
-assign vm_cal = vm_data2[0];
 
 // vm Combinational Logic
 assign irq_vm_rdy = vm_ready_reg;

flows/makefile.ASIC

@@ -24,3 +24,6 @@ syn_TS:
 syn_VM:
 	@mkdir -p ./imp/VM
 	@cd asic/VM;  dc_shell -f dc_synthesis.tcl
+
+clean_all_syn:
+	rm -rf ./imp

verif/VM_integration/vm_integration_tests.py

@@ -164,13 +164,13 @@ async def VM_run_once_irq(dut,tb):
 
 async def VM_set_an(dut,tb,n):
     tb.log.info("Set voltage input to %d",n)
-    reg0 = await tb.config_ahb_master.read(0x00,4)
-    reg0 = int(reg0[0]['data'],16)
-    reg0 = reg0 & 0xFFFFFF0F
-    reg0 = reg0 | (1<<7) 
-    reg0 = reg0 | (n<<4)   
-    await tb.config_ahb_master.write(0x00,reg0)
-    await wait_reg0_write(dut,tb)
+    reg2 = await tb.config_ahb_master.read(0x08,4)
+    reg2 = int(reg2[0]['data'],16)
+    reg2 = reg2 & 0xFFFFFFF0
+    reg2 = reg2 | (1<<3) 
+    reg2 = reg2 | (n)   
+    await tb.config_ahb_master.write(0x08,reg2)
+    await wait_reg2_write(dut,tb)
 
 @cocotb.test()
 async def VM_test1(dut):