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Commit 421e52c8 authored by Daniel Newbrook's avatar Daniel Newbrook
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IP_wrappers/synopsys_PD_sensor_integration.v 0 → 100644
+ 288
− 0
View file @ 421e52c8
module synopsys_PD_sensor_integration(
input wire PCLK,
input wire aRESETn,
input wire PSELx,
input wire [1:0] PADDR,
input wire PENABLE,
input wire [2:0] PPROT,
input wire [3:0] PSTRB,
input wire PWRITE,
input wire [31:0] PWDATA,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output wire irq_pd_rdy
);
// APB Logic
// APB interface
localparam APB_IDLE = 3'd0,
APB_WRITE = 3'd1,
APB_READ = 3'd2;
reg [1:0] apb_current_state;
reg [1:0] apb_next_state;
reg PSLVERR_reg;
reg [31:0] PRDATA_reg;
assign PRDATA = PRDATA_reg;
assign PSLVERR = PSLVERR_reg;
// PD Signals
wire pd_clk;
reg pd_clk_slow;
wire [11:0] pd_data;
wire pd_faultn;
// PD Irq registers
wire pd_ready;
reg pd_ready_reg;
reg pd_ready_reg_clr;
reg pd_irq_enabled;
reg pd_irq_clear_reg;
reg pd_irq_rdy_reg;
// PD Enable
reg pd_enable_reg;
reg pd_clk_gate_reg;
reg [7:0] pd_clk_div;
reg pd_local_reset;
// PD Configuration
reg [7:0] pd_config_reg1;
reg [7:0] pd_config_reg2;
reg [7:0] pd_config_reg3;
reg pd_cload;
// PD Conversion
reg pd_run_reg;
reg pd_run_clear;
reg pd_run_continuous_reg;
// PD Combinational Logic
assign irq_pd_rdy = pd_irq_rdy_reg;
// Main sequential logic
always @(posedge PCLK or negedge aRESETn)begin
if(~aRESETn) begin
// Software Definable
pd_enable_reg <= 1'b0;
pd_clk_div <= 8'd7; // 100MHz/(7*2) = 7.1MHz (max 8 MHz)
pd_config_reg1 <= 8'h00; // Parallel mode, Process detector speed mode
pd_config_reg2 <= 8'hC0; // Built in delay chain
pd_config_reg3 <= 8'h21; // W=63 A=32
pd_cload <= 1'b0;
pd_irq_clear_reg <= 1'b0;
pd_irq_enabled <= 1'b0;
pd_run_reg <= 1'b0;
pd_run_continuous_reg <= 1'b0;
pd_ready_reg_clr <= 1'b0;
// Automatically controlled registers
pd_irq_rdy_reg <= 1'b0;
pd_ready_reg <= 1'b0;
// APB Control
apb_current_state <= APB_IDLE;
apb_next_state <= APB_IDLE;
PSLVERR_reg <= 1'b0;
end
else begin
if(pd_irq_enabled && pd_ready)
pd_irq_rdy_reg <= 1'b1;
if(pd_irq_clear_reg)
pd_irq_rdy_reg <= 1'b0;
if(pd_run_continuous_reg)
pd_run_reg <= 1'b1;
if(pd_run_clear) begin
pd_run_clear <= 1'b0;
pd_run_reg <= 1'b0;
end
if(pd_ready)
pd_ready_reg <= 1'b1;
if(pd_ready_reg_clr) begin
pd_ready_reg_clr <= 1'b0;
pd_ready_reg <= 1'b0;
end
// APB control
apb_current_state <= apb_next_state;
end
end
// Clock Gating
always @(negedge PCLK) begin
pd_clk_gate_reg <= pd_enable_reg;
end
assign pd_clk = PCLK & pd_clk_gate_reg;
reg [7:0] pd_clk_div_counter;
always @(posedge pd_clk or negedge aRESETn) begin
if(~aRESETn) begin
pd_clk_div_counter <= 8'd0;
pd_clk_slow <= 1'b0;
end else begin
pd_clk_div_counter <= pd_clk_div_counter + 8'd1;
if(pd_clk_div_counter >= pd_clk_div) begin
pd_clk_slow <= ~pd_clk_slow;
pd_clk_div_counter <= 8'd0;
end
end
end
reg [2:0] pd_reset_delay;
reg pd_run_delay;
always @(posedge pd_clk_slow or negedge aRESETn) begin
if(~aRESETn) begin
pd_local_reset <= 1'b0;
pd_reset_delay <= 3'h0;
pd_run_clear <= 1'b0;
pd_run_delay <= 1'b0;
end else begin
if(~pd_run_continuous_reg & pd_run_reg)
pd_run_delay <= 1'b1;
if(pd_run_delay) begin
pd_run_delay <= 1'b0;
pd_run_clear <= 1'b1;
end
if(~pd_local_reset)
pd_reset_delay <= pd_reset_delay + 1'b1;
if(pd_reset_delay>=3'h6)
pd_local_reset <= 1'b1;
end
end
always @(*) begin
case(apb_current_state)
APB_IDLE: begin
PSLVERR_reg = 1'b0;
if(PSELx) begin
if(PWRITE) begin
apb_next_state = APB_WRITE;
end else begin
apb_next_state = APB_READ;
end
end
else begin
apb_next_state = APB_IDLE;
end
end
APB_WRITE: begin
case(PADDR)
10'h000: begin
if(PSTRB[0]==1'b1) begin
pd_enable_reg = PWDATA[0];
pd_run_reg = PWDATA[1];
pd_run_continuous_reg = PWDATA[2];
pd_ready_reg_clr = PWDATA[3];
end
if(PSTRB[1]==1'b1) begin
pd_clk_div = PWDATA[15:8];
end
if(PSTRB[2]==1'b1) begin
pd_irq_enabled = PWDATA[16];
pd_irq_clear_reg = PWDATA[17];
end
end
2'h1: PSLVERR_reg = 1'b1; // Data Reg - read only
2'h2: begin // Test Control
if(PSTRB[0]==1'b1) begin
pd_config_reg1 = PWDATA[7:0];
end
if(PSTRB[1]==1'b1) begin
pd_config_reg2 = PWDATA[15:8];
end
if(PSTRB[2]==1'b1) begin
pd_config_reg3 = PWDATA[23:16];
end
if(PSTRB[3]==1'b1) begin
pd_cload = PWDATA[24];
end
end
2'h3: PSLVERR_reg = 1'b1; // ID Reg - read only
endcase
apb_next_state = APB_IDLE;
end
APB_READ: begin
case(PADDR)
2'h0: PRDATA_reg = {7'h00, pd_ready_reg, 6'h0, pd_irq_clear_reg, pd_irq_enabled, pd_clk_div, 3'h0, pd_local_reset, pd_ready_reg_clr, pd_run_continuous_reg, pd_run_reg, pd_enable_reg};
2'h1: PRDATA_reg = {30'h0, pd_data};
2'h2: PRDATA_reg = {7'h0, pd_cload, pd_config_reg3, pd_config_reg2, pd_config_reg1}; // Configuration
2'h3: PRDATA_reg = 32'h736E7064; // ID Reg
endcase
apb_next_state = APB_IDLE;
end
default: apb_next_state = APB_IDLE;
endcase
end
assign PREADY = (apb_current_state==APB_READ|apb_current_state==APB_WRITE)? 1'b1:1'b0;
mr74125 u_synopsys_pd(
`ifdef MR74125_GATE_PW_SIM
.VDD(),
.VDDA(),
.VSS(),
`endif
.clk(pd_clk_slow),
.run(pd_run_reg),
.rstn(pd_local_reset),
.cload(pd_cload),
.cfg1_0(pd_config_reg1[0]),
.cfg1_1(pd_config_reg1[1]),
.cfg1_2(pd_config_reg1[2]),
.cfg1_3(pd_config_reg1[3]),
.cfg1_4(pd_config_reg1[4]),
.cfg1_5(pd_config_reg1[5]),
.cfg1_6(pd_config_reg1[6]),
.cfg1_7(pd_config_reg1[7]),
.cfg2_0(pd_config_reg2[0]),
.cfg2_1(pd_config_reg2[1]),
.cfg2_2(pd_config_reg2[2]),
.cfg2_3(pd_config_reg2[3]),
.cfg2_4(pd_config_reg2[4]),
.cfg2_5(pd_config_reg2[5]),
.cfg2_6(pd_config_reg2[6]),
.cfg2_7(pd_config_reg2[7]),
.cfg3_0(pd_config_reg3[0]),
.cfg3_1(pd_config_reg3[1]),
.cfg3_2(pd_config_reg3[2]),
.cfg3_3(pd_config_reg3[3]),
.cfg3_4(pd_config_reg3[4]),
.cfg3_5(pd_config_reg3[5]),
.cfg3_6(pd_config_reg3[6]),
.cfg3_7(pd_config_reg3[7]),
.scan_in(1'b0),
.scan_en(1'b0),
.scan_test(1'b0),
.dout0(pd_data[0]),
.dout1(pd_data[1]),
.dout2(pd_data[2]),
.dout3(pd_data[3]),
.dout4(pd_data[4]),
.dout5(pd_data[5]),
.dout6(pd_data[6]),
.dout7(pd_data[7]),
.dout8(pd_data[8]),
.dout9(pd_data[9]),
.dout10(pd_data[10]),
.dout11(pd_data[11]),
.rdy(pd_ready),
.dout_type(),
.faultn(pd_faultn),
.scan_out()
);
endmodule
\ No newline at end of file
IP_wrappers/synopsys_TS_sensor_integration.v 0 → 100644
+ 280
− 0
View file @ 421e52c8
// To DO
// - Calibration mode signals
// - Signature mode
// - Test control
module synopsys_TS_sensor_integration(
input wire PCLK,
input wire aRESETn,
input wire PSELx,
input wire [1:0] PADDR,
input wire PENABLE,
input wire [2:0] PPROT,
input wire [3:0] PSTRB,
input wire PWRITE,
input wire [31:0] PWDATA,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
input wire ts_vcal,
inout wire [3:0] ts_an_test,
output wire ts_vss_sense,
output wire irq_ts_rdy
);
// APB Logic
// APB interface
localparam APB_IDLE = 3'd0,
APB_WRITE = 3'd1,
APB_READ = 3'd2;
reg [1:0] apb_current_state;
reg [1:0] apb_next_state;
reg PSLVERR_reg;
reg [31:0] PRDATA_reg;
assign PRDATA = PRDATA_reg;
assign PSLVERR = PSLVERR_reg;
// TS signals
wire ts_clk;
reg ts_clk_slow;
wire [11:0] ts_data;
// TS Irq registers
wire ts_ready;
reg ts_ready_reg;
reg ts_ready_reg_clr;
reg ts_irq_enabled;
reg ts_irq_clear_reg;
reg ts_irq_rdy_reg;
// TS Enable
reg ts_enable_reg;
reg ts_clk_gate_reg;
reg [7:0] ts_clk_div;
reg ts_local_reset;
// TS conversion
reg ts_run_reg;
reg ts_run_clear;
reg ts_run_continuous_reg;
// TS test modes
reg ts_sig_en;
reg [3:0] ts_tm_an;
reg ts_cal;
// TS Combination logic
assign irq_ts_rdy = ts_irq_rdy_reg;
// Main sequential logic
always @(posedge PCLK or negedge aRESETn)begin
if(~aRESETn) begin
// Synopsys TS register control logic
// Software definable
ts_irq_clear_reg <= 1'b0; //Clear interrupt
ts_irq_enabled <= 1'b0; //Enable interrupt
ts_run_reg <= 1'b0;
ts_enable_reg <= 1'b0; //Enable Temperature sensor
ts_run_continuous_reg <= 1'b0;
ts_clk_div <= 8'd24;
ts_ready_reg_clr <= 1'b0;
ts_sig_en <= 1'b0;
ts_tm_an <= 4'h0;
ts_cal <= 1'b0;
// Automatically controlled registers
ts_irq_rdy_reg <= 1'b0;
ts_ready_reg <= 1'b0;
// APB Control
apb_current_state <= APB_IDLE;
apb_next_state <= APB_IDLE;
PSLVERR_reg <= 1'b0;
end
else begin
// Synopsys TS register control logic
if(ts_irq_enabled && ts_ready)
ts_irq_rdy_reg <= 1'b1;
if (ts_irq_clear_reg)
ts_irq_rdy_reg <= 1'b0;
if(ts_run_continuous_reg)
ts_run_reg <= 1'b1;
if(ts_run_clear) begin
ts_run_clear <= 1'b0;
ts_run_reg <= 1'b0;
end
if(ts_ready)
ts_ready_reg <= 1'b1;
if(ts_ready_reg_clr) begin
ts_ready_reg_clr <= 1'b0;
ts_ready_reg <= 1'b0;
end
// APB control
apb_current_state <= apb_next_state;
end
end
// Clock gating
always @(negedge PCLK) begin
ts_clk_gate_reg <= ts_enable_reg;
end
assign ts_clk = PCLK & ts_clk_gate_reg;
reg [7:0] ts_clk_div_counter;
always @(posedge ts_clk or negedge aRESETn) begin
if(~aRESETn) begin
ts_clk_div_counter <= 8'd0;
ts_clk_slow <=1'b0;
end else begin
ts_clk_div_counter <= ts_clk_div_counter + 8'd1;
if(ts_clk_div_counter >= ts_clk_div) begin
ts_clk_slow <= ~ts_clk_slow;
ts_clk_div_counter <= 8'd0;
end
end
end
reg [2:0] ts_reset_delay;
reg ts_run_delay;
always @(posedge ts_clk_slow or negedge aRESETn) begin
if(~aRESETn) begin
ts_local_reset <= 1'b0;
ts_run_clear <= 1'b0;
ts_reset_delay <= 3'h0;
ts_run_delay <= 1'b0;
end else begin
if(~ts_run_continuous_reg & ts_run_reg)
ts_run_delay <= 1'b1;
if(ts_run_delay) begin
ts_run_delay <= 1'b0;
ts_run_clear <= 1'b1;
end
if(~ts_local_reset)
ts_reset_delay <= ts_reset_delay + 1'b1;
if(ts_reset_delay>=3'h6)
ts_local_reset <= 1'b1;
end
end
always @(*) begin
case(apb_current_state)
APB_IDLE: begin
PSLVERR_reg = 1'b0;
if(PSELx) begin
if(PWRITE) begin
apb_next_state = APB_WRITE;
end else begin
apb_next_state = APB_READ;
end
end
else begin
apb_next_state = APB_IDLE;
end
end
APB_WRITE: begin
case(PADDR)
10'h000: begin
if(PSTRB[0]==1'b1) begin
ts_enable_reg = PWDATA[0];
ts_run_reg = PWDATA[1];
ts_run_continuous_reg = PWDATA[2];
ts_ready_reg_clr = PWDATA[3];
end
if(PSTRB[1]==1'b1) begin
ts_clk_div = PWDATA[15:8];
end
if(PSTRB[2]==1'b1) begin
ts_irq_enabled = PWDATA[16];
ts_irq_clear_reg = PWDATA[17];
end
end
2'h1: PSLVERR_reg = 1'b1; // Data Reg - read only
2'h2: begin // Test Control
if(PSTRB[0]==1'b1) begin
ts_cal=PWDATA[0];
end
if(PSTRB[1]==1'b1) begin
ts_sig_en = PWDATA[8];
end
if(PSTRB[2]==1'b1) begin
ts_tm_an = PWDATA[16];
end
end
2'h3: PSLVERR_reg = 1'b1; // ID Reg - read only
endcase
apb_next_state = APB_IDLE;
end
APB_READ: begin
case(PADDR)
2'h0: PRDATA_reg = {7'h00, ts_ready_reg, 6'h0, ts_irq_clear_reg, ts_irq_enabled, ts_clk_div, 3'h0, ts_local_reset, ts_ready_reg_clr, ts_run_continuous_reg, ts_run_reg, ts_enable_reg};
2'h1: PRDATA_reg = {{20{1'b0}}, ts_data}; // Data Reg
2'h2: PRDATA_reg = {8'h00, 7'h00, ts_tm_an, 7'h00, ts_sig_en, 7'h00, ts_cal}; // Test Control
2'h3: PRDATA_reg = 32'h736E7473; // ID Reg
endcase
apb_next_state = APB_IDLE;
end
default: apb_next_state = APB_IDLE;
endcase
end
assign PREADY = (apb_current_state==APB_READ|apb_current_state==APB_WRITE)? 1'b1:1'b0;
mr74127 u_synopsys_ts(
`ifdef MR74127_GATE_PW_SIM
.VDD(), // Digital supply
.VDDA(), // Analog supply
.VSS(), // Combined ground
`endif
.clk(ts_clk_slow), // TS Clock
.pd(~ts_enable_reg), // TS Power Down Control (active high)
.run(ts_run_reg), // TS Run (active high)
.rstn(ts_local_reset), // TS Reset (active low)
.vcal(ts_vcal), // TS Analog calibration voltage
.cal(ts_cal), // TS Enable for analog trim (active high)
.ser_en(1'b0), // TS Serial data output enable (active high)
.sgn_en(ts_sig_en), // TS Signature enable (active high)
.tm_an0(ts_tm_an[0]), // TS Test access control - bit 0 (LSB)
.tm_an1(ts_tm_an[1]), // TS Test access control - bit 1 (LSB)
.tm_an2(ts_tm_an[2]), // TS Test access control - bit 2 (LSB)
.tm_an3(ts_tm_an[3]), // TS Test access control - bit 3 (LSB)
.rdy(ts_ready), // TS Ready (active high)
.dout0(ts_data[0]), // TS Data Out - bit 0 (LSB)
.dout1(ts_data[1]), // TS Data Out - bit 1
.dout2(ts_data[2]), // TS Data Out - bit 2
.dout3(ts_data[3]), // TS Data Out - bit 3
.dout4(ts_data[4]), // TS Data Out - bit 4
.dout5(ts_data[5]), // TS Data Out - bit 5
.dout6(ts_data[6]), // TS Data Out - bit 6
.dout7(ts_data[7]), // TS Data Out - bit 7
.dout8(ts_data[8]), // TS Data Out - bit 8
.dout9(ts_data[9]), // TS Data Out - bit 9
.dout10(ts_data[10]), // TS Data Out - bit 10
.dout11(ts_data[11]), // TS Data Out - bit 11 (MSB)
.digo(), // TS Bitstream Out
.an_test0(ts_an_test[0]), // TS Analog test access - signal 0
.an_test1(ts_an_test[1]), // TS Analog test access - signal 1
.an_test2(ts_an_test[2]), // TS Analog test access - signal 2
.an_test3(ts_an_test[3]), // TS Analog test access - signal 3
.vss_sense(ts_vss_sense) // vss sense (for cal)
);
endmodule
\ No newline at end of file
IP_wrappers/synopsys_VM_sensor_integration.v 0 → 100644
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− 0
View file @ 421e52c8
module synopsys_VM_sensor_integration(
input wire PCLK,
input wire aRESETn,
input wire PSELx,
input wire [1:0] PADDR,
input wire PENABLE,
input wire [2:0] PPROT,
input wire [3:0] PSTRB,
input wire PWRITE,
input wire [31:0] PWDATA,
output wire [31:0] PRDATA,
output wire PREADY,
output wire PSLVERR,
output wire irq_vm_rdy
);
endmodule
flist/synopsys_pvt_ip.flist 0 → 100644
+ 11
− 0
View file @ 421e52c8
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/subsystem_wrappers/nanosoc_sysio_snps_pvt_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/IP_wrappers/synopsys_TS_sensor_integration.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/synopsys_28nm_slm_integration/IP_wrappers/synopsys_PD_sensor_integration.v
+incdir+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b/model/verilog/
/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/1.01b/model/verilog/mr74127.v
+incdir+/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a/model/verilog
/home/dwn1c21/SoC-Labs/Synopsys_ip/IP/Southampton_28hpcp_pd_vm_ts_vmps_pvtc/dwc_sensors_pd_tsmc28hpcp_1.00a/synopsys/dwc_sensors_pd_tsmc28hpcp/1.00a/model/verilog/mr74125.v
subsystem_wrappers/nanosoc_sysio_snps_pvt_ss.v 0 → 100644
+ 512
− 0
View file @ 421e52c8
module nanosoc_sysio_snps_pvt_ss #(
parameter SNPS_PVT_TS_0_ENABLE=0,
parameter SNPS_PVT_TS_1_ENABLE=0,
parameter SNPS_PVT_TS_2_ENABLE=0,
parameter SNPS_PVT_TS_3_ENABLE=0,
parameter SNPS_PVT_TS_4_ENABLE=0,
parameter SNPS_PVT_TS_5_ENABLE=0,
parameter SNPS_PVT_PD_0_ENABLE=0,
parameter SNPS_PVT_VM_0_ENABLE=0,
// If peripherals are generated with asynchronous clock domain to HCLK of the processor
// You might need to add synchroniser to the IRQ signal.
// In this example APB subsystem, the IRQ synchroniser is used to all peripherals
// when the INCLUDE_IRQ_SYNCHRONIZER parameter is set to 1. In practice you may have
// some IRQ signals need to be synchronised and some do not.
parameter INCLUDE_IRQ_SYNCHRONIZER=0,
// By default the APB subsystem include a simple test slave use in ARM for
// validation purpose. You can remove this test slave by setting the
// INCLUDE_APB_TEST_SLAVE paramater to 0,
parameter INCLUDE_APB_TEST_SLAVE = 1,
// Big endian - Add additional endian conversion logic to support big endian.
// (for ARM internal testing and evaluation of the processor in
// big endian configuration).
// 0 = little endian, 1 = big endian
//
// The example systems including this APB subsystem are designed as
// little endian. Most of the peripherals and memory system are
// little endian. This parameter is introduced to allows ARM to
// perform system level tests to verified behaviour of bus
// components in big endian configuration, and to allow designers
// to evaluate the processor in big endian configuration.
//
// Use of this parameter is not recommended for actual product
// development as this adds extra hardware. For big endian systems
// ideally the peripherals should be modified to use a big endian
// programmer's model.
parameter BE = 0)(
input wire TS_VCAL,
output wire TS_VSS_SENSE,
inout wire [3:0] TS_AN_TEST,
output wire [5:0] irq_ts_rdy,
output wire irq_pd_rdy,
output wire irq_vm_rdy,
input wire HCLK,
input wire HRESETn,
input wire HSEL,
input wire [15:0] HADDR,
input wire [1:0] HTRANS,
input wire HWRITE,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HREADY,
input wire [31:0] HWDATA,
output wire HREADYOUT,
output wire [31:0] HRDATA,
output wire HRESP,
input wire PCLK, // Peripheral clock
input wire PCLKG, // Gate PCLK for bus interface only
input wire PCLKEN, // Clock divider for AHB to APB bridge
input wire PRESETn // APB reset
);
// --------------------------------------------------------------------------
// Internal wires
// --------------------------------------------------------------------------
wire [15:0] i_paddr;
wire i_psel;
wire i_penable;
wire i_pwrite;
wire [2:0] i_pprot;
wire [3:0] i_pstrb;
wire [31:0] i_pwdata;
// wire from APB slave mux to APB bridge
wire i_pready_mux;
wire [31:0] i_prdata_mux;
wire i_pslverr_mux;
wire snps_PVT_ts0_psel;
wire snps_PVT_ts0_pready;
wire [31:0] snps_PVT_ts0_prdata;
wire snps_PVT_ts0_pslverr;
wire snps_PVT_ts1_psel;
wire snps_PVT_ts1_pready;
wire [31:0] snps_PVT_ts1_prdata;
wire snps_PVT_ts1_pslverr;
wire snps_PVT_ts2_psel;
wire snps_PVT_ts2_pready;
wire [31:0] snps_PVT_ts2_prdata;
wire snps_PVT_ts2_pslverr;
wire snps_PVT_ts3_psel;
wire snps_PVT_ts3_pready;
wire [31:0] snps_PVT_ts3_prdata;
wire snps_PVT_ts3_pslverr;
wire snps_PVT_ts4_psel;
wire snps_PVT_ts4_pready;
wire [31:0] snps_PVT_ts4_prdata;
wire snps_PVT_ts4_pslverr;
wire snps_PVT_ts5_psel;
wire snps_PVT_ts5_pready;
wire [31:0] snps_PVT_ts5_prdata;
wire snps_PVT_ts5_pslverr;
wire snps_PVT_pd0_psel;
wire snps_PVT_pd0_pready;
wire [31:0] snps_PVT_pd0_prdata;
wire snps_PVT_pd0_pslverr;
wire snps_PVT_vm0_psel;
wire snps_PVT_vm0_pready;
wire [31:0] snps_PVT_vm0_prdata;
wire snps_PVT_vm0_pslverr;
// endian handling
wire bigendian;
assign bigendian = (BE!=0) ? 1'b1 : 1'b0;
wire [31:0] hwdata_le; // Little endian write data
wire [31:0] hrdata_le; // Little endian read data
wire reg_be_swap_ctrl_en = HSEL & HTRANS[1] & HREADY & bigendian;
reg [1:0] reg_be_swap_ctrl; // registered byte swap control
wire [1:0] nxt_be_swap_ctrl; // next state of byte swap control
assign nxt_be_swap_ctrl[1] = bigendian & (HSIZE[1:0]==2'b10); // Swap upper and lower half word
assign nxt_be_swap_ctrl[0] = bigendian & (HSIZE[1:0]!=2'b00); // Swap byte within hafword
// Register byte swap control for data phase
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_be_swap_ctrl <= 2'b00;
else if (reg_be_swap_ctrl_en)
reg_be_swap_ctrl <= nxt_be_swap_ctrl;
end
// swap byte within half word
wire [31:0] hwdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
{HWDATA[23:16],HWDATA[31:24],HWDATA[7:0],HWDATA[15:8]}:
{HWDATA[31:24],HWDATA[23:16],HWDATA[15:8],HWDATA[7:0]};
// swap lower and upper half word
assign hwdata_le = (reg_be_swap_ctrl[1] & bigendian) ?
{hwdata_mux_1[15: 0],hwdata_mux_1[31:16]}:
{hwdata_mux_1[31:16],hwdata_mux_1[15:0]};
// swap byte within half word
wire [31:0] hrdata_mux_1 = (reg_be_swap_ctrl[0] & bigendian) ?
{hrdata_le[23:16],hrdata_le[31:24],hrdata_le[ 7:0],hrdata_le[15:8]}:
{hrdata_le[31:24],hrdata_le[23:16],hrdata_le[15:8],hrdata_le[7:0]};
// swap lower and upper half word
assign HRDATA = (reg_be_swap_ctrl[1] & bigendian) ?
{hrdata_mux_1[15: 0],hrdata_mux_1[31:16]}:
{hrdata_mux_1[31:16],hrdata_mux_1[15:0]};
// AHB to APB bus bridge
cmsdk_ahb_to_apb
#(.ADDRWIDTH (16),
.REGISTER_RDATA (1),
.REGISTER_WDATA (0))
u_ahb_to_apb(
// AHB side
.HCLK (HCLK),
.HRESETn (HRESETn),
.HSEL (HSEL),
.HADDR (HADDR[15:0]),
.HTRANS (HTRANS),
.HSIZE (HSIZE),
.HPROT (HPROT),
.HWRITE (HWRITE),
.HREADY (HREADY),
.HWDATA (hwdata_le),
.HREADYOUT(HREADYOUT), // AHB Outputs
.HRDATA (hrdata_le),
.HRESP (HRESP),
.PADDR (i_paddr[15:0]),
.PSEL (i_psel),
.PENABLE (i_penable),
.PSTRB (i_pstrb),
.PPROT (i_pprot),
.PWRITE (i_pwrite),
.PWDATA (i_pwdata),
.APBACTIVE(APBACTIVE),
.PCLKEN (PCLKEN), // APB clock enable signal
.PRDATA (i_prdata_mux),
.PREADY (i_pready_mux),
.PSLVERR (i_pslverr_mux)
);
cmsdk_apb_slave_mux #(
.PORT0_ENABLE (SNPS_PVT_TS_0_ENABLE),
.PORT1_ENABLE (SNPS_PVT_TS_1_ENABLE),
.PORT2_ENABLE (SNPS_PVT_TS_2_ENABLE),
.PORT3_ENABLE (SNPS_PVT_TS_3_ENABLE),
.PORT4_ENABLE (SNPS_PVT_TS_4_ENABLE),
.PORT5_ENABLE (SNPS_PVT_TS_5_ENABLE),
.PORT6_ENABLE (SNPS_PVT_PD_0_ENABLE),
.PORT7_ENABLE (SNPS_PVT_VM_0_ENABLE),
.PORT8_ENABLE (0),
.PORT9_ENABLE (0),
.PORT10_ENABLE (0),
.PORT11_ENABLE (0),
.PORT12_ENABLE (0),
.PORT13_ENABLE (0),
.PORT14_ENABLE (0),
.PORT15_ENABLE (0)
) u_apb_PVT_slave_mux (
// Inputs
.DECODE4BIT (i_paddr[7:4]),
.PSEL (i_psel),
// PSEL (output) and return status & data (inputs) for each port
.PSEL0 (snps_PVT_ts0_psel),
.PREADY0 (snps_PVT_ts0_pready),
.PRDATA0 (snps_PVT_ts0_prdata),
.PSLVERR0 (snps_PVT_ts0_pslverr),
.PSEL1 (snps_PVT_ts1_psel),
.PREADY1 (snps_PVT_ts1_pready),
.PRDATA1 (snps_PVT_ts1_prdata),
.PSLVERR1 (snps_PVT_ts1_pslverr),
.PSEL2 (snps_PVT_ts2_psel),
.PREADY2 (snps_PVT_ts2_pready),
.PRDATA2 (snps_PVT_ts2_prdata),
.PSLVERR2 (snps_PVT_ts2_pslverr),
.PSEL3 (snps_PVT_ts3_psel),
.PREADY3 (snps_PVT_ts3_pready),
.PRDATA3 (snps_PVT_ts3_prdata),
.PSLVERR3 (snps_PVT_ts3_pslverr),
.PSEL4 (snps_PVT_ts4_psel),
.PREADY4 (snps_PVT_ts4_pready),
.PRDATA4 (snps_PVT_ts4_prdata),
.PSLVERR4 (snps_PVT_ts4_pslverr),
.PSEL5 (snps_PVT_ts5_psel),
.PREADY5 (snps_PVT_ts5_pready),
.PRDATA5 (snps_PVT_ts5_prdata),
.PSLVERR5 (snps_PVT_ts5_pslverr),
.PSEL6 (snps_PVT_pd0_psel),
.PREADY6 (snps_PVT_pd0_pready),
.PRDATA6 (snps_PVT_pd0_prdata),
.PSLVERR6 (snps_PVT_pd0_pslverr),
.PSEL7 (snps_PVT_vm0_psel),
.PREADY7 (snps_PVT_vm0_pready),
.PRDATA7 (snps_PVT_vm0_prdata),
.PSLVERR7 (snps_PVT_vm0_pslverr),
.PSEL8 (psel8),
.PREADY8 (1'b1),
.PRDATA8 (32'h00000000),
.PSLVERR8 (1'b1),
.PSEL9 (psel9),
.PREADY9 (1'b1),
.PRDATA9 (32'h00000000),
.PSLVERR9 (1'b1),
.PSEL10 (psel10),
.PREADY10 (1'b1),
.PRDATA10 (32'h00000000),
.PSLVERR10 (1'b1),
.PSEL11 (psel11),
.PREADY11 (1'b1),
.PRDATA11 (32'h00000000),
.PSLVERR11 (1'b1),
.PSEL12 (psel12),
.PREADY12 (1'b1),
.PRDATA12 (32'h00000000),
.PSLVERR12 (1'b1),
.PSEL13 (psel13),
.PREADY13 (1'b1),
.PRDATA13 (32'h00000000),
.PSLVERR13 (1'b1),
.PSEL14 (psel14),
.PREADY14 (1'b1),
.PRDATA14 (32'h00000000),
.PSLVERR14 (1'b1),
.PSEL15 (psel15),
.PREADY15 (1'b1),
.PRDATA15 (32'h00000000),
.PSLVERR15 (1'b1),
// Output
.PREADY (i_pready_mux),
.PRDATA (i_prdata_mux),
.PSLVERR (i_pslverr_mux)
);
generate if(SNPS_PVT_TS_0_ENABLE==1)begin: gen_snps_PVT_ts0
synopsys_TS_sensor_integration u_snps_PVT_ts0(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts0_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts0_prdata),
.PREADY(snps_PVT_ts0_pready),
.PSLVERR(snps_PVT_ts0_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[0])
);
end else begin: gen_no_snps_PVT_ts0
assign snps_PVT_ts0_prdata = {32{1'b0}};
assign snps_PVT_ts0_pready = 1'b1;
assign snps_PVT_ts0_pslverr = 1'b1;
assign irq_ts_rdy[0] = 1'b0;
end endgenerate
generate if(SNPS_PVT_TS_1_ENABLE==1)begin: gen_snps_PVT_ts1
synopsys_TS_sensor_integration u_snps_PVT_ts1(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts1_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts1_prdata),
.PREADY(snps_PVT_ts1_pready),
.PSLVERR(snps_PVT_ts1_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[1])
);
end else begin: gen_no_snps_PVT_ts1
assign snps_PVT_ts1_prdata = {32{1'b0}};
assign snps_PVT_ts1_pready = 1'b1;
assign snps_PVT_ts1_pslverr = 1'b1;
assign irq_ts_rdy[1] = 1'b0;
end endgenerate
generate if(SNPS_PVT_TS_2_ENABLE==1)begin: gen_snps_PVT_ts2
synopsys_TS_sensor_integration u_snps_PVT_ts2(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts2_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts2_prdata),
.PREADY(snps_PVT_ts2_pready),
.PSLVERR(snps_PVT_ts2_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[2])
);
end else begin: gen_no_snps_PVT_ts2
assign snps_PVT_ts2_prdata = {32{1'b0}};
assign snps_PVT_ts2_pready = 1'b1;
assign snps_PVT_ts2_pslverr = 1'b1;
assign irq_ts_rdy[2] = 1'b0;
end endgenerate
generate if(SNPS_PVT_TS_3_ENABLE==1)begin: gen_snps_PVT_ts3
synopsys_TS_sensor_integration u_snps_PVT_ts3(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts3_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts3_prdata),
.PREADY(snps_PVT_ts3_pready),
.PSLVERR(snps_PVT_ts3_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[3])
);
end else begin: gen_no_snps_PVT_ts3
assign snps_PVT_ts3_prdata = {32{1'b0}};
assign snps_PVT_ts3_pready = 1'b1;
assign snps_PVT_ts3_pslverr = 1'b1;
assign irq_ts_rdy[3] = 1'b0;
end endgenerate
generate if(SNPS_PVT_TS_4_ENABLE==1)begin: gen_snps_PVT_ts4
synopsys_TS_sensor_integration u_snps_PVT_ts4(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts4_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts4_prdata),
.PREADY(snps_PVT_ts4_pready),
.PSLVERR(snps_PVT_ts4_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[4])
);
end else begin: gen_no_snps_PVT_ts4
assign snps_PVT_ts4_prdata = {32{1'b0}};
assign snps_PVT_ts4_pready = 1'b1;
assign snps_PVT_ts4_pslverr = 1'b1;
assign irq_ts_rdy[4] = 1'b0;
end endgenerate
generate if(SNPS_PVT_TS_5_ENABLE==1)begin: gen_snps_PVT_ts5
synopsys_TS_sensor_integration u_snps_PVT_ts5(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_ts5_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_ts5_prdata),
.PREADY(snps_PVT_ts5_pready),
.PSLVERR(snps_PVT_ts5_pslverr),
.ts_vcal(TS_VCAL),
.ts_an_test(TS_AN_TEST),
.ts_vss_sense(TS_VSS_SENSE),
.irq_ts_rdy(irq_ts_rdy[5])
);
end else begin: gen_no_snps_PVT_ts5
assign snps_PVT_ts5_prdata = {32{1'b0}};
assign snps_PVT_ts5_pready = 1'b1;
assign snps_PVT_ts5_pslverr = 1'b1;
assign irq_ts_rdy[5] = 1'b0;
end endgenerate
generate if(SNPS_PVT_PD_0_ENABLE==1)begin: gen_snps_PVT_pd0
synopsys_PD_sensor_integration u_snps_PVT_pd0(
.PCLK(PCLK),
.aRESETn(HRESETn),
.PSELx(snps_PVT_pd0_psel),
.PADDR(i_paddr[3:2]),
.PENABLE(i_penable),
.PPROT(i_pprot),
.PSTRB(i_pstrb),
.PWRITE(i_pwrite),
.PWDATA(i_pwdata),
.PRDATA(snps_PVT_pd0_prdata),
.PREADY(snps_PVT_pd0_pready),
.PSLVERR(snps_PVT_pd0_pslverr),
.irq_pd_rdy(irq_pd_rdy)
);
end else begin: gen_no_snps_PVT_pd0
assign snps_PVT_pd0_prdata = {32{1'b0}};
assign snps_PVT_pd0_pready = 1'b1;
assign snps_PVT_pd0_pslverr = 1'b1;
assign irq_pd_rdy = 1'b0;
end endgenerate
generate if(SNPS_PVT_VM_0_ENABLE==1)begin: gen_snps_PVT_vm0
end else begin: gen_no_snps_PVT_vm0
assign snps_PVT_vm0_prdata = {32{1'b0}};
assign snps_PVT_vm0_pready = 1'b1;
assign snps_PVT_vm0_pslverr = 1'b1;
assign irq_vm_rdy = 1'b0;
end endgenerate
endmodule
\ No newline at end of file
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