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  • soclabs/soctools_flow
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bin/filelist_compile.py
View file @ 1f17b470
......@@ -113,7 +113,7 @@ def read_list(filelist, first, incdirs, args):
elif args.makefile == True:
compiled_filelist.append("VERILOG_SOURCES += " + str(line_list[1]).replace("$","$env")+"/"+str(file))
else:
compiled_filelist.append("read_verilog " + str(line_list[1])+"/"+str(file))
compiled_filelist.append("read_verilog " + str(env_var_substitute(line_list[1], tcl=True)).replace("$","$env")+"/"+str(file))
else:
compiled_filelist.append(line_list[1]+"/"+str(file))
......