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SoCLabs
SoCDebug Tech
Commits
05781fa353a8918c8206e9cc10b7e8aaef5203aa
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2
main
default
protected
feat_extio
2 results
socdebug_tech
controller
verilog
socdebug_usrt_control.v
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authors
dam1n19
dam1n19
dwf1m12
dwf1m12
dwn1c21
dwn1c21
eb3u21
eb3u21
hhp1n22
hhp1n22
John Darlington
JohnD
6 authors
Oct 02, 2024
refactor socdebug for extio8x4 integration
· 05781fa3
dwf1m12
authored
7 months ago
05781fa3
Jul 10, 2023
fix floating RX stream ready output
· aa64ace1
dwf1m12
authored
1 year ago
aa64ace1
Jun 03, 2023
Restructured Debug Controller
· 5a418341
David Mapstone
authored
1 year ago
5a418341
Update Name to SoCDebug
· 33fb0d88
David Mapstone
authored
1 year ago
33fb0d88
Jun 02, 2023
Started Moving IP into Repo
· db6019d6
dam1n19
authored
1 year ago
db6019d6
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dwf1m12 authored
dwf1m12 authored
