Added makeflow for packaged ft1248 controller

flist/f232h_ft1248_stream_ip.flist

@@ -12,7 +12,5 @@
 // Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
 //-----------------------------------------------------------------------------
 
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
-$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/wrappers/uart_axi_master/verilog/uart_axi_master.v
\ No newline at end of file
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/ft232h_ft1248_stream/verilog/SYNCHRONIZER_EDGES.v

fpga/makefile

@@ -43,37 +43,72 @@ clean_socket:
 
 
 # UART Packaging
-DESIGN_VC := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/uart_axi_master_ip.flist
+UART_FLIST := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/uart_axi_master_ip.flist
 
 IMPLEMENTATION_DIR   ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
 RUN_DIR              := $(IMPLEMENTATION_DIR)/run
 IMP_SOCKET_DIR       := $(IMPLEMENTATION_DIR)/socket
-IMP_UART_AXI_M_DIR   := $(IMP_SOCKET_DIR)/uart_axi_master
 
-TCL_FLIST_DIR        := $(IMP_UART_AXI_M_DIR)/flist
-TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
 
-COMPONENT_TOP        := uart_axi_master
-VENDOR               := ultraembedded
-CORE_REV             ?= 1
 
-# Environment Variables for Packaging NanoSoC
-package_uart: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
-package_uart: export FPGA_COMPONENT_LIB      = $(IMP_UART_AXI_M_DIR)
-package_uart: export FPGA_COMPONENT_TOP      = $(COMPONENT_TOP)
-package_uart: export FPGA_VENDOR             = $(VENDOR)
-package_uart: export FPGA_CORE_REV           = $(CORE_REV)
+UART_IMP_DIR              := $(IMP_SOCKET_DIR)/uart_axi_master
+UART_TCL_FLIST_DIR        := $(UART_IMP_DIR)/flist
+UART_TCL_OUTPUT_FILELIST  := $(UART_TCL_FLIST_DIR)/gen_flist.tcl
+
+UART_TOP        := uart_axi_master
+UART_VENDOR     := ultraembedded
+UART_CORE_REV   ?= 1
+
 
 flist_uart:
-	@mkdir -p $(TCL_FLIST_DIR)
+	@mkdir -p $(UART_TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
-	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_UART_AXI_M_DIR);)
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(UART_FLIST) -o $(UART_TCL_OUTPUT_FILELIST) -r $(UART_IMP_DIR);)
+	
+# Environment Variables for Packaging NanoSoC
+package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST)
+package_uart: export FPGA_COMPONENT_LIB      = $(UART_IMP_DIR)
+package_uart: export FPGA_COMPONENT_TOP      = $(UART_TOP)
+package_uart: export FPGA_VENDOR             = $(VENDUART_VENDOROR)
+package_uart: export FPGA_CORE_REV           = $(UART_CORE_REV)
 	
 # Package NanoSoC IP
 package_uart: flist_uart
 	@echo Packaging UART to AXI Master Component
 	@mkdir -p $(RUN_DIR)
 	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
-	@mkdir -p $(IMP_UART_AXI_M_DIR)/logs
-	@cp $(RUN_DIR)/vivado.log $(IMP_UART_AXI_M_DIR)/logs
-	@echo UART to AXI Master Packaged
\ No newline at end of file
+	@mkdir -p $(UART_IMP_DIR)/logs
+	@cp $(RUN_DIR)/vivado.log $(UART_IMP_DIR)/logs
+	@echo UART to AXI Master Packaged
+
+# UART Packaging
+F232H_FLIST    := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/f232h_ft1248_stream_ip.flist
+F232H_IMP_DIR  := $(IMP_SOCKET_DIR)/f232h_ft1248_stream
+
+F232H_TCL_FLIST_DIR        := $(F232H_IMP_DIR)/flist
+F232H_TCL_OUTPUT_FILELIST  := $(F232H_TCL_FLIST_DIR)/gen_flist.tcl
+
+F232H_TOP                  := ft232h_ft1248_stream
+F232H_VENDOR               := soclabs.org
+F232H_CORE_REV             ?= 1
+
+flist_f232h:
+	@mkdir -p $(F232H_TCL_FLIST_DIR)
+	@(cd $(F232H_TCL_FLIST_DIR); \
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(F232H_FLIST) -o $(F232H_TCL_OUTPUT_FILELIST) -r $(F232H_IMP_DIR);)
+	
+# Environment Variables for Packaging NanoSoC
+package_f232h: export FPGA_COMPONENT_FILELIST = $(F232H_TCL_OUTPUT_FILELIST)
+package_f232h: export FPGA_COMPONENT_LIB      = $(F232H_IMP_DIR)
+package_f232h: export FPGA_COMPONENT_TOP      = $(F232H_TOP)
+package_f232h: export FPGA_VENDOR             = $(F232H_VENDOR)
+package_f232h: export FPGA_CORE_REV           = $(F232H_CORE_REV)
+	
+# Package NanoSoC IP
+package_f232h: flist_f232h
+	@echo Packaging F232H FT1248 to AXI Stream Component
+	@mkdir -p $(RUN_DIR)
+	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
+	@mkdir -p $(F232H_IMP_DIR)/logs
+	@cp $(RUN_DIR)/vivado.log $(F232H_IMP_DIR)/logs
+	@echo F232H FT1248 to AXI Stream Packaged
\ No newline at end of file

socket/ft232h_ft1248_stream/verilog/ft232h_ft1248_stream.v

@@ -15,17 +15,17 @@
 
  module ft232h_ft1248_stream #
  (
-         // Users to add parameters here
+    // Users to add parameters here
 
-         // User parameters ends
-         // Do not modify the parameters beyond this line
+    // User parameters ends
+    // Do not modify the parameters beyond this line
 
 
-         // Parameters of Axi Stream Bus Interface rxd8
-         parameter integer C_rxd8_TDATA_WIDTH    = 8,
+    // Parameters of Axi Stream Bus Interface rxd8
+    parameter integer C_rxd8_TDATA_WIDTH    = 8,
 
-         // Parameters of Axi Stream Bus Interface txd8
-         parameter integer C_txd8_TDATA_WIDTH    = 8
+    // Parameters of Axi Stream Bus Interface txd8
+    parameter integer C_txd8_TDATA_WIDTH    = 8
  )
   (
   input  wire  ft_clk_i,         // SCLK