SoCShute is a Debug Controller to enable low-level debug within SoCs. SoCShute runs over both FT1248 and USRT allowing for access to the internal system bus. Currently we have only supported an AHB interface but we may expand this in the future.
## RTL Structure
This repo will contain the Verilog RTL for the USRT, FT1248 Controller and the ADP Controller. These components communicate with each other over AXI-Stream Interfaces which allow for the addition of other AXI-Stream compatable Debug Communication interfaces to interact with the ADP Controller.
## Getting started
## FPGA Debug Infrastructure
### RTL
Socket Debug interface IP is also contained within the repo to allow for debug access even within and FPGA environemnt without needing to directly memory map your SoC - this can be useful when considering an ASIC tapeout for your SoC. We have packaged this up for use within Vivado and this is something we are looking to publish to this repo.
To make it easy for you to get started with GitLab, here's a list of recommended next steps.
Already a pro? Just edit this README.md and make it your own. Want to make it easy? [Use the template at the bottom](#editing-this-readme)!
## Add your files
-[ ] [Create](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#create-a-file) or [upload](https://docs.gitlab.com/ee/user/project/repository/web_editor.html#upload-a-file) files
-[ ] [Add files using the command line](https://docs.gitlab.com/ee/gitlab-basics/add-file.html#add-a-file-using-the-command-line) or push an existing Git repository with the following command:
-[ ] [Set up project integrations](https://git.soton.ac.uk/soclabs/socshute-tech/-/settings/integrations)
## Collaborate with your team
-[ ] [Invite team members and collaborators](https://docs.gitlab.com/ee/user/project/members/)
-[ ] [Create a new merge request](https://docs.gitlab.com/ee/user/project/merge_requests/creating_merge_requests.html)
-[ ] [Automatically close issues from merge requests](https://docs.gitlab.com/ee/user/project/issues/managing_issues.html#closing-issues-automatically)
-[ ] [Automatically merge when pipeline succeeds](https://docs.gitlab.com/ee/user/project/merge_requests/merge_when_pipeline_succeeds.html)
## Test and Deploy
Use the built-in continuous integration in GitLab.
-[ ] [Get started with GitLab CI/CD](https://docs.gitlab.com/ee/ci/quick_start/index.html)
-[ ] [Analyze your code for known vulnerabilities with Static Application Security Testing(SAST)](https://docs.gitlab.com/ee/user/application_security/sast/)
-[ ] [Deploy to Kubernetes, Amazon EC2, or Amazon ECS using Auto Deploy](https://docs.gitlab.com/ee/topics/autodevops/requirements.html)
-[ ] [Use pull-based deployments for improved Kubernetes management](https://docs.gitlab.com/ee/user/clusters/agent/)
-[ ] [Set up protected environments](https://docs.gitlab.com/ee/ci/environments/protected_environments.html)
***
# Editing this README
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### Python Interface
As well as this, a python library to allow access to the Socket will be provided which will allow Memory reads and writes to occur from a Host Python computer over a UART connection to the FPGA board. The plan is for these libraries to be compatable with an ASIC tester board.
