Added target for compiling UART to AXI Master component

flist/uart_axi_master.flist

+//-----------------------------------------------------------------------------
+// SoCDebug UART to AXI Master Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Ultraembedded UART to AXI Master IP
+//-----------------------------------------------------------------------------
+
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_fifo.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge_uart.v
+$(SOCLABS_SOCDEBUG_TECH_DIR)/socket/uart_axi_master/src_v/dbg_bridge.v
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fpga/makefile

@@ -35,8 +35,45 @@ package_uart_to_axi:
 	@mkdir -p $(IMP_SOCKET_DIR)
 	@cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(IMP_SOCKET_DIR)/uart_to_AXI_master_1.0
 
-package_socket: clean_socket package_uart_to_axi package_ft1248_to_stream package_axi_stream_io package_adp_control
+package_socket: clean_socket package_uart package_ft1248_to_stream package_axi_stream_io package_adp_control
 
 clean_socket:
 	@echo Cleaning FPGA Implementation Socket Directory
-	@rm -rf $(IMP_SOCKET_DIR)
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+	@rm -rf $(IMP_SOCKET_DIR)
+
+
+
+DESIGN_VC := $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/uart_axi_master.flist
+
+IMPLEMENTATION_DIR   ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
+RUN_DIR              := $(IMPLEMENTATION_DIR)/run
+IMP_SOCKET_DIR       := $(IMPLEMENTATION_DIR)/socket
+IMP_UART_AXI_M_DIR   := $(IMP_SOCKET_DIR)/uart_axi_master
+
+TCL_FLIST_DIR        := $(IMP_UART_AXI_M_DIR)/flist
+TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
+
+COMPONENT_TOP        := dbg_bridge
+VENDOR               := ultraembedded
+CORE_REV             ?= 1
+
+# Environment Variables for Packaging NanoSoC
+package_uart: export FPGA_COMPONENT_FILELIST = $(TCL_OUTPUT_FILELIST)
+package_uart: export FPGA_COMPONENT_LIB      = $(IMP_UART_AXI_M_DIR)
+package_uart: export FPGA_COMPONENT_TOP      = $(COMPONENT_TOP)
+package_uart: export FPGA_VENDOR             = $(VENDOR)
+package_uart: export FPGA_CORE_REV           = $(CORE_REV)
+
+flist_uart:
+	@mkdir -p $(TCL_FLIST_DIR)
+	@(cd $(TCL_FLIST_DIR); \
+	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_UART_AXI_M_DIR);)
+	
+# Package NanoSoC IP
+package_uart: flist_uart
+	@echo Packaging UART to AXI Master Component
+	@mkdir -p $(RUN_DIR)
+	@cd $(RUN_DIR); vivado -mode batch -source $(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/fpga/package_component.tcl
+	@mkdir -p $(IMP_UART_AXI_M_DIR)/logs
+	@cp $(RUN_DIR)/vivado.log $(IMP_UART_AXI_M_DIR)/logs
+	@echo UART to AXI Master Packaged
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