add programmable divider register[7:0] output for pre-scalar, and clean up redundant logic

controller/verilog/socdebug_usrt_control.v

@@ -89,6 +89,8 @@ module socdebug_usrt_control (
   input  wire [7:0]  RX_DATA8_i,
   output wire        RX_READY_o,
 
+  output wire [7:0]  INVBAUDDIV8_o,
+
   output wire        TXINT,    // Transmit Interrupt
   output wire        RXINT,    // Receive Interrupt
   output wire        TXOVRINT, // Transmit overrun Interrupt
@@ -110,8 +112,6 @@ localparam  ARM_CMSDK_APB_UART_CID2 = 8'h05;
 localparam  ARM_CMSDK_APB_UART_CID3 = 8'hb1;
 
 // original external IOs
-wire        RXD = 1'b1; // Serial input
-wire        TXD;      // Transmit data output
 wire        TXEN;     // Transmit enabled
 wire        BAUDTICK; // Baud rate (x16) Tick
   
@@ -138,6 +138,8 @@ reg     [7:0] reg_tx_buf;     // Transmit data buffer
 reg     [7:0] reg_rx_buf;     // Receive data buffer
 reg    [19:0] reg_baud_div;   // Baud rate setting
 
+assign INVBAUDDIV8_o = ~reg_baud_div[7:0];
+
 // Internal signals
   // Baud rate divider
 reg    [15:0] reg_baud_cntr_i; // baud rate divider counter i (integer)
@@ -169,44 +171,13 @@ wire    [1:0] intr_stat_set;   // Set TX/RX interrupt
 wire    [1:0] intr_stat_clear; // Clear TX/RX interrupt
 
   // transmit
-reg     [3:0] tx_state;    // Transmit FSM state
-reg     [4:0] nxt_tx_state;
-wire          tx_state_update;
-wire          tx_state_inc; // Bit pulse
-reg     [3:0] tx_tick_cnt;  // Transmit Tick counter
-wire    [4:0] nxt_tx_tick_cnt;
-reg     [7:0] tx_shift_buf;      // Transmit shift register
-wire    [7:0] nxt_tx_shift_buf;  // next state    for tx_shift_buf
-wire          tx_buf_ctrl_shift; // shift control for tx_shift_buf
-wire          tx_buf_ctrl_load;  // load  control for tx_shift_buf
 reg           tx_buf_full;  // TX Buffer full
-reg           reg_txd;      // Tx Data
-wire          nxt_txd;      // next state of reg_txd
-wire          update_reg_txd; // update reg_txd
-wire          tx_buf_clear; // Clear buffer full status when data is load into TX shift register
-
-  // Receive data sync and filter
-reg           rxd_sync_1;  // Double flip-flop syncrhoniser
-reg           rxd_sync_2;  // Double flip-flop syncrhoniser
-reg     [2:0] rxd_lpf;     // Averaging Low Pass Filter
-wire    [2:0] nxt_rxd_lpf;
-wire          rx_shift_in; // Shift Register Input
 
   // Receiver
-reg     [3:0] rx_state;   // Receiver FSM state
-reg     [4:0] nxt_rx_state;
-wire          rx_state_update;
-reg     [3:0] rx_tick_cnt; // Receiver Tick counter
-wire    [4:0] nxt_rx_tick_cnt;
-wire          update_rx_tick_cnt;
-wire          rx_state_inc;// Bit pulse
-reg     [6:0] rx_shift_buf;// Receiver shift data register
-wire    [6:0] nxt_rx_shift_buf;
 reg           rx_buf_full;  // Receive buffer full status
 wire          nxt_rx_buf_full;
 wire          rxbuf_sample; // Sample received data into receive data buffer
 wire          rx_data_read; // Receive data buffer read by APB interface
-wire    [7:0] nxt_rx_buf;
 
 // Start of main code
 // Read and write control signals
@@ -422,7 +393,6 @@ assign  write_enable10 = write_enable & (PADDR[11:2] == 10'h004);
   assign tx_overrun = tx_buf_full & write_enable00;
 
   // Connect to external
-  assign TXD  = reg_txd;
   assign TXEN = reg_ctrl[0];