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Commit 1abba52d authored by dam1n19's avatar dam1n19
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Fixed UART vendor variable

parent 2e9197ff
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...@@ -70,7 +70,7 @@ flist_uart: ...@@ -70,7 +70,7 @@ flist_uart:
package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST) package_uart: export FPGA_COMPONENT_FILELIST = $(UART_TCL_OUTPUT_FILELIST)
package_uart: export FPGA_COMPONENT_LIB = $(UART_IMP_DIR) package_uart: export FPGA_COMPONENT_LIB = $(UART_IMP_DIR)
package_uart: export FPGA_COMPONENT_TOP = $(UART_TOP) package_uart: export FPGA_COMPONENT_TOP = $(UART_TOP)
package_uart: export FPGA_VENDOR = $(VENDUART_VENDOROR) package_uart: export FPGA_VENDOR = $(UART_VENDOR)
package_uart: export FPGA_CORE_REV = $(UART_CORE_REV) package_uart: export FPGA_CORE_REV = $(UART_CORE_REV)
# Package UART to AXI Master IP # Package UART to AXI Master IP
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