Fix flist bugs and trig ports on big

config/cfg_xhb_axi_to_ahb_big.cfg

+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Release Information : DMA350-r0p0-00rel0
+#
+# -----------------------------------------------------------------------------
+#  Abstract : Configuration file for XHB-500 AXI to AHB Bridge
+# -----------------------------------------------------------------------------
+
+# -----------------------------
+# User Configuration
+# -----------------------------
+
+
+
+#
+# COMPONENT: Name of the component to configure.
+#     Valid values:
+#         [xhb500_ahb_to_axi_bridge, xhb500_axi_to_ahb_bridge]
+#
+COMPONENT: xhb500_axi_to_ahb_bridge
+
+
+#
+# CONFIG_NAME: Name of the configuration.
+#     Each unifiqued element and top is suffixed with
+#     _${CONFIG_NAME}
+#
+CONFIG_NAME: sldma350
+
+
+#
+# ADDR_WIDTH: Address Bus width
+#     Valid values:
+#         [32]
+ADDR_WIDTH: 32
+
+#
+# DATA_WIDTH: Data Bus width
+#     Valid values:
+#         [32,64,128,256,512,1024]
+DATA_WIDTH: 32
+
+
+#
+# USER_AX_WIDTH: Address channel user signal width
+#     When set to 0, the signals are not not present on the generated RTL
+#     Valid values:
+#         0-256
+USER_AX_WIDTH: 0
+
+
+#
+# USER_W_WIDTH: Write channel user signal width
+#     When set to 0, the signals are not not present on the generated RTL
+#     Valid values:
+#         0-256
+USER_W_WIDTH: 0
+
+#
+# USER_R_WIDTH: Read channel user signal width
+#     When set to 0, the signals are not not present on the generated RTL
+#     Valid values:
+#         0-256
+USER_R_WIDTH: 0
+
+
+#
+# ID_WIDTH: AXI ID and HMASTER port width
+#     Valid values:
+#         1-32
+ID_WIDTH: 2
+
+
+#
+# REGISTER_x_CNTRL: Registers AHB address and control / read data signals
+#     Valid values:
+#         [ON,OFF]
+REGISTER_AHB_CNTRL: OFF
+REGISTER_AHB_RDATA: OFF
+
+
+# REGISTER_AXI_x: Adds register slice to AXI AW/AR/W/R/B channel
+#     Valid values:
+#         - BYPASS  : no register slice
+#         - FORWARD : registers valid and payload path
+#         - REVERSE : registers ready path
+#         - FULL    : registers both directions
+REGISTER_AXI_AW: BYPASS
+REGISTER_AXI_AR: BYPASS
+REGISTER_AXI_W:  BYPASS
+REGISTER_AXI_R:  BYPASS
+REGISTER_AXI_B:  BYPASS
+
+# LB_WIDTH: Width of the user loopback signals on AXI interface
+#     Valid values:
+#         - 0..8
+LB_WIDTH: 0
+
+#HWSTRB_ENABLE: Enables hwstrb output, disables awsparse input and vice-versa. Disabled ports are removed.
+#     Valid values:
+#         - OFF : Uses AWSPARSE input
+#         - ON  : Adds HWSTRB output
+HWSTRB_ENABLE: ON
+
+#
+# Qx_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
+#     Valid values:
+#         - OFF : no synchronizer
+#         - ON  : added synchronizer
+QCLK_SYNC_EN: ON
+

flist/dma350_ahb_big_ip.flist

@@ -53,6 +53,9 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_grant_
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
 
++incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/
+
+
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
@@ -62,13 +65,16 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_chan
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_wr_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_2d_rd_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_inc_gen_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_wrapper_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_slave_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_stream_master_sldma350.sv
@@ -85,13 +91,16 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_chan
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_wr_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_2d_rd_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_inc_gen_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_wrapper_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_slave_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_stream_master_sldma350.sv
@@ -99,6 +108,7 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_chan
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
 
+
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350_pkg.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_gen_regif_dmach_2_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_gen_regmap_dmach_2_sldma350.sv
@@ -108,13 +118,16 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_chan
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_2d_wr_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_2d_rd_ctrl_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_fifo_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_cmdlink_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_rd_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_wr_if_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_axi_stop_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_inc_gen_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_wrapper_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_slave_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_stream_master_sldma350.sv
@@ -122,7 +135,6 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_chan
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_in_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_2_sldma350/verilog/ada_channel_2_trig_out_sldma350.sv
 
-
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv

flist/sldma350_ahb_big.flist

@@ -37,5 +37,5 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/veril
 $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_strbgen.sv
 
 
-$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_ahb_small.v
+$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_ahb_big.v
 $(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_trig_converter.v

makefile

@@ -47,7 +47,7 @@ config_dma_ahb_small:
 	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb.cfg --output ./src/
 config_dma_ahb_big:
 	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb_big.yaml --output ./src/
-	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb.cfg --output ./src/
+	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb_big.cfg --output ./src/
 
 clean_ip:
 	@rm -rf ./src/*
\ No newline at end of file