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Commit 5e360a60 authored by Daniel Newbrook's avatar Daniel Newbrook
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Update DMA AHB

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config/cfg_dma_ahb.yaml
+ 2
− 2
View file @ 5e360a60
...@@ -87,8 +87,8 @@ CH_STREAM_MASK: 0x3 ...@@ -87,8 +87,8 @@ CH_STREAM_MASK: 0x3
# #
# Valid values: # Valid values:
# [1,2,4,8,16,32,64] # [1,2,4,8,16,32,64]
CH_0_FIFO_DEPTH: 2 CH_0_FIFO_DEPTH: 32
CH_1_FIFO_DEPTH: 2 CH_1_FIFO_DEPTH: 32
# #
# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel. # CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
......
config/cfg_xhb_axi_to_ahb.cfg 0 → 100755
+ 123
− 0
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#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#----------------------------------------------------------------------------
#
# Release Information : DMA350-r0p0-00rel0
#
# -----------------------------------------------------------------------------
# Abstract : Configuration file for XHB-500 AXI to AHB Bridge
# -----------------------------------------------------------------------------
# -----------------------------
# User Configuration
# -----------------------------
#
# COMPONENT: Name of the component to configure.
# Valid values:
# [xhb500_ahb_to_axi_bridge, xhb500_axi_to_ahb_bridge]
#
COMPONENT: xhb500_axi_to_ahb_bridge
#
# CONFIG_NAME: Name of the configuration.
# Each unifiqued element and top is suffixed with
# _${CONFIG_NAME}
#
CONFIG_NAME: sldma350
#
# ADDR_WIDTH: Address Bus width
# Valid values:
# [32]
ADDR_WIDTH: 32
#
# DATA_WIDTH: Data Bus width
# Valid values:
# [32,64,128,256,512,1024]
DATA_WIDTH: 32
#
# USER_AX_WIDTH: Address channel user signal width
# When set to 0, the signals are not not present on the generated RTL
# Valid values:
# 0-256
USER_AX_WIDTH: 0
#
# USER_W_WIDTH: Write channel user signal width
# When set to 0, the signals are not not present on the generated RTL
# Valid values:
# 0-256
USER_W_WIDTH: 0
#
# USER_R_WIDTH: Read channel user signal width
# When set to 0, the signals are not not present on the generated RTL
# Valid values:
# 0-256
USER_R_WIDTH: 0
#
# ID_WIDTH: AXI ID and HMASTER port width
# Valid values:
# 1-32
ID_WIDTH: 1
#
# REGISTER_x_CNTRL: Registers AHB address and control / read data signals
# Valid values:
# [ON,OFF]
REGISTER_AHB_CNTRL: OFF
REGISTER_AHB_RDATA: OFF
# REGISTER_AXI_x: Adds register slice to AXI AW/AR/W/R/B channel
# Valid values:
# - BYPASS : no register slice
# - FORWARD : registers valid and payload path
# - REVERSE : registers ready path
# - FULL : registers both directions
REGISTER_AXI_AW: BYPASS
REGISTER_AXI_AR: BYPASS
REGISTER_AXI_W: BYPASS
REGISTER_AXI_R: BYPASS
REGISTER_AXI_B: BYPASS
# LB_WIDTH: Width of the user loopback signals on AXI interface
# Valid values:
# - 0..8
LB_WIDTH: 0
#HWSTRB_ENABLE: Enables hwstrb output, disables awsparse input and vice-versa. Disabled ports are removed.
# Valid values:
# - OFF : Uses AWSPARSE input
# - ON : Adds HWSTRB output
HWSTRB_ENABLE: ON
#
# Qx_SYNC_EN: Add 2 DFF synchronizer on inputs of clock Q-channel
# Valid values:
# - OFF : no synchronizer
# - ON : added synchronizer
QCLK_SYNC_EN: ON
flist/dma350_ip.flist
+ 21
− 21
View file @ 5e360a60
...@@ -18,6 +18,27 @@ ...@@ -18,6 +18,27 @@
// ============= DMA-350 search path ============= // ============= DMA-350 search path =============
+incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ +incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_interface_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_flop.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_sync.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_mux2.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_or.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_idbit_v1.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_ecorevnum.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
...@@ -102,25 +123,4 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldm ...@@ -102,25 +123,4 @@ $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldm
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_interface_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_flop.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_sync.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_mux2.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_or.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_idbit_v1.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_ecorevnum.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv $(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv
flist/sldma350.flist 0 → 100644
+ 41
− 0
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//-----------------------------------------------------------------------------
// MegaSoC DMA-350 Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// Daniel Newbrook (d.newbrook@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for Arm DMA-350
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/dma350_ip.flist
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_or.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_xor.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_flop.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/xhb500_sync.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_bypass_regd_slice_empty.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/xhb500_regd_slice/verilog/xhb500_forward_regd_slice_empty.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_pkg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_xin.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_core_h_xout.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_xreg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_hreg.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_r.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_respreg_b.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_lpi.sv
$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/xhb500_axi_to_ahb_bridge_sldma350/verilog/xhb500_axi_to_ahb_bridge_sldma350_strbgen.sv
$(SOCLABS_SLDMA350_TECH_DIR)/wrapper/logical/sldma350_ahb.v
makefile
+ 1
− 0
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...@@ -41,6 +41,7 @@ config_dma_axi: ...@@ -41,6 +41,7 @@ config_dma_axi:
@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_axi.yaml --output ./src/ @$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_axi.yaml --output ./src/
config_dma_ahb: config_dma_ahb:
@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb.yaml --output ./src/ @$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb.yaml --output ./src/
@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb.cfg --output ./src/
clean_ip: clean_ip:
@rm -rf ./src/* @rm -rf ./src/*
\ No newline at end of file
wrapper/logical/sldma350_ahb.v
+ 209
− 198
View file @ 5e360a60
...@@ -13,7 +13,7 @@ ...@@ -13,7 +13,7 @@
module sldma350_ahb #( module sldma350_ahb #(
parameter SYS_ADDR_W = 32, parameter SYS_ADDR_W = 32,
parameter SYS_DATA_W = 32, parameter SYS_DATA_W = 32,
parameter CFG_ADDR_W = 12, // Configuration Port Address Width parameter CFG_ADDR_W = 13, // Configuration Port Address Width
parameter CHANNEL_NUM = 2 // Number of DMA Channels parameter CHANNEL_NUM = 2 // Number of DMA Channels
)( )(
...@@ -42,7 +42,8 @@ module sldma350_ahb #( ...@@ -42,7 +42,8 @@ module sldma350_ahb #(
input wire [CFG_ADDR_W-1:0] PADDR, // APB address input wire [CFG_ADDR_W-1:0] PADDR, // APB address
input wire [SYS_DATA_W-1:0] PWDATA, // APB write data input wire [SYS_DATA_W-1:0] PWDATA, // APB write data
output wire [SYS_DATA_W-1:0] PRDATA, // APB read data output wire [SYS_DATA_W-1:0] PRDATA, // APB read data
output wire PREADY,
output wire PSLVERR,
// DMA Request and Status Port // DMA Request and Status Port
input wire [CHANNEL_NUM-1:0] DMA_REQ, // DMA transfer request input wire [CHANNEL_NUM-1:0] DMA_REQ, // DMA transfer request
output wire [CHANNEL_NUM-1:0] DMA_DONE, // DMA transfer done output wire [CHANNEL_NUM-1:0] DMA_DONE, // DMA transfer done
...@@ -50,139 +51,133 @@ module sldma350_ahb #( ...@@ -50,139 +51,133 @@ module sldma350_ahb #(
); );
wire SYS_HRESETn, wire SYS_HRESETn;
wire DMAC_PCLKen, wire DMAC_ACLKen;
wire DMAC_ACLKen,
// Q Channel Signals // Q Channel Signals
wire DMAC_CLK_QREQN, wire DMAC_CLK_QREQN;
wire DMAC_CLK_QACCEPTN, wire DMAC_CLK_QACCEPTN;
wire DMAC_CLK_QDENY, wire DMAC_CLK_QDENY;
wire DMAC_CLK_QACTIVE, wire DMAC_CLK_QACTIVE;
// P Channel Signals // P Channel Signals
wire DMAC_PREQ, wire DMAC_PREQ;
wire [3:0] DMAC_PSTATE, wire [3:0] DMAC_PSTATE;
wire DMAC_PACCEPT, wire DMAC_PACCEPT;
wire DMAC_PDENY, wire DMAC_PDENY;
wire [9:0] DMAC_PACTIVE, wire [9:0] DMAC_PACTIVE;
wire DMAC_PWAKEUP, wire DMAC_PWAKEUP;
wire DMAC_PDEBUG, wire DMAC_PDEBUG;
wire DMAC_PSEL,
wire DMAC_PENABLE,
wire [2:0] DMAC_PPROT,
wire DMAC_PWRITE,
wire [12:0] DMAC_PADDR,
wire [31:0] DMAC_PWDATA,
wire [3:0] DMAC_PSTRB,
wire DMAC_PREADY,
wire DMAC_PSLVERR,
wire [31:0] DMAC_PRDATA,
// DMAC AXI Port // DMAC AXI Port
wire DMAC_AWAKEUP, wire DMAC_AWAKEUP;
wire DMAC_AWVALID, wire DMAC_AWVALID;
wire [SYS_ADDR_W-1:0] DMAC_AWADDR, wire [SYS_ADDR_W-1:0] DMAC_AWADDR;
wire [1:0] DMAC_AWBURST, wire [1:0] DMAC_AWBURST;
wire [7:0] DMAC_AWLEN, wire [7:0] DMAC_AWLEN;
wire [2:0] DMAC_AWSIZE, wire [2:0] DMAC_AWSIZE;
wire [3:0] DMAC_AWQOS, wire [3:0] DMAC_AWQOS;
wire [2:0] DMAC_AWPROT, wire [2:0] DMAC_AWPROT;
wire DMAC_AWREADY, wire DMAC_AWREADY;
wire [3:0] DMAC_AWCACHE, wire [3:0] DMAC_AWCACHE;
wire [3:0] DMAC_AWINNER, wire [3:0] DMAC_AWINNER;
wire [1:0] DMAC_AWDOMAIN, wire [1:0] DMAC_AWDOMAIN;
wire DMAC_ARVALID, wire DMAC_ARVALID;
wire [SYS_ADDR_W-1:0] DMAC_ARADDR, wire [SYS_ADDR_W-1:0] DMAC_ARADDR;
wire [1:0] DMAC_ARBURST, wire [1:0] DMAC_ARBURST;
wire [7:0] DMAC_ARLEN, wire [7:0] DMAC_ARLEN;
wire [2:0] DMAC_ARSIZE, wire [2:0] DMAC_ARSIZE;
wire [3:0] DMAC_ARQOS, wire [3:0] DMAC_ARQOS;
wire [2:0] DMAC_ARPROT, wire [2:0] DMAC_ARPROT;
wire DMAC_ARREADY, wire DMAC_ARREADY;
wire [3:0] DMAC_ARCACHE, wire [3:0] DMAC_ARCACHE;
wire [3:0] DMAC_ARINNER, wire [3:0] DMAC_ARINNER;
wire [1:0] DMAC_ARDOMAIN, wire [1:0] DMAC_ARDOMAIN;
wire DMAC_ARCMDLINK, wire DMAC_ARCMDLINK;
wire DMAC_WVALID, wire DMAC_WVALID;
wire DMAC_WLAST, wire DMAC_WLAST;
wire [16-1:0] DMAC_WSTRB, wire [4-1:0] DMAC_WSTRB;
wire [SYS_DATA_W-1:0] DMAC_WDATA, wire [SYS_DATA_W-1:0] DMAC_WDATA;
wire DMAC_WREADY, wire DMAC_WREADY;
wire DMAC_RVALID, wire DMAC_RVALID;
wire DMAC_RLAST, wire DMAC_RLAST;
wire [SYS_DATA_W-1:0] DMAC_RDATA, wire [SYS_DATA_W-1:0] DMAC_RDATA;
wire [2-1:0] DMAC_RPOISON, wire [2-1:0] DMAC_RPOISON;
wire [1:0] DMAC_RRESP, wire [1:0] DMAC_RRESP;
wire DMAC_RREADY, wire DMAC_RREADY;
wire DMAC_BVALID, wire DMAC_BVALID;
wire [1:0] DMAC_BRESP, wire [1:0] DMAC_BRESP;
wire DMAC_BREADY, wire DMAC_BREADY;
wire DMAC_BID;
wire DMAC_WID;
wire DMAC_RID;
wire DMAC_ARID;
wire DMAC_AWID;
// Trigger 0 in // Trigger 0 in
wire DMAC_TRIG_IN_0_REQ, wire DMAC_TRIG_IN_0_REQ;
wire [1:0] DMAC_TRIG_IN_0_REQ_TYPE, wire [1:0] DMAC_TRIG_IN_0_REQ_TYPE;
wire DMAC_TRIG_IN_0_ACK, wire DMAC_TRIG_IN_0_ACK;
wire [1:0] DMAC_TRIG_IN_0_ACK_TYPE, wire [1:0] DMAC_TRIG_IN_0_ACK_TYPE;
wire DMAC_TRIG_IN_1_REQ, wire DMAC_TRIG_IN_1_REQ;
wire [1:0] DMAC_TRIG_IN_1_REQ_TYPE, wire [1:0] DMAC_TRIG_IN_1_REQ_TYPE;
wire DMAC_TRIG_IN_1_ACK, wire DMAC_TRIG_IN_1_ACK;
wire [1:0] DMAC_TRIG_IN_1_ACK_TYPE, wire [1:0] DMAC_TRIG_IN_1_ACK_TYPE;
wire DMAC_TRIG_OUT_0_REQ, wire DMAC_TRIG_OUT_0_REQ;
wire DMAC_TRIG_OUT_0_ACK, wire DMAC_TRIG_OUT_0_ACK;
wire DMAC_TRIG_OUT_1_REQ, wire DMAC_TRIG_OUT_1_REQ;
wire DMAC_TRIG_OUT_1_ACK, wire DMAC_TRIG_OUT_1_ACK;
wire [2-1:0] DMAC_IRQ_CHANNEL, wire [2-1:0] DMAC_IRQ_CHANNEL;
wire DMAC_IRQ_COMB_NONSEC, wire DMAC_IRQ_COMB_NONSEC;
// DMAC Channel 0 AXI stream out // DMAC Channel 0 AXI stream out
wire DMAC_STR_OUT_0_TVALID, wire DMAC_STR_OUT_0_TVALID;
wire DMAC_STR_OUT_0_TREADY, wire DMAC_STR_OUT_0_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA, wire [SYS_DATA_W-1:0] DMAC_STR_OUT_0_TDATA;
wire [16-1:0] DMAC_STR_OUT_0_TSTRB, wire [16-1:0] DMAC_STR_OUT_0_TSTRB;
wire DMAC_STR_OUT_0_TLAST, wire DMAC_STR_OUT_0_TLAST;
// DMAC Channel 0 AXI Stream in // DMAC Channel 0 AXI Stream in
wire DMAC_STR_IN_0_TVALID, wire DMAC_STR_IN_0_TVALID;
wire DMAC_STR_IN_0_TREADY, wire DMAC_STR_IN_0_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA, wire [SYS_DATA_W-1:0] DMAC_STR_IN_0_TDATA;
wire [16-1:0] DMAC_STR_IN_0_TSTRB, wire [16-1:0] DMAC_STR_IN_0_TSTRB;
wire DMAC_STR_IN_0_TLAST, wire DMAC_STR_IN_0_TLAST;
wire DMAC_STR_IN_0_FLUSH, wire DMAC_STR_IN_0_FLUSH;
// DMAC Channel 1 AXI Stream out // DMAC Channel 1 AXI Stream out
wire DMAC_STR_OUT_1_TVALID, wire DMAC_STR_OUT_1_TVALID;
wire DMAC_STR_OUT_1_TREADY, wire DMAC_STR_OUT_1_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA, wire [SYS_DATA_W-1:0] DMAC_STR_OUT_1_TDATA;
wire [16-1:0] DMAC_STR_OUT_1_TSTRB, wire [16-1:0] DMAC_STR_OUT_1_TSTRB;
wire DMAC_STR_OUT_1_TLAST, wire DMAC_STR_OUT_1_TLAST;
// DMAC Channel 1 AXI Stream out // DMAC Channel 1 AXI Stream out
wire DMAC_STR_IN_1_TVALID, wire DMAC_STR_IN_1_TVALID;
wire DMAC_STR_IN_1_TREADY, wire DMAC_STR_IN_1_TREADY;
wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA, wire [SYS_DATA_W-1:0] DMAC_STR_IN_1_TDATA;
wire [16-1:0] DMAC_STR_IN_1_TSTRB, wire [16-1:0] DMAC_STR_IN_1_TSTRB;
wire DMAC_STR_IN_1_TLAST, wire DMAC_STR_IN_1_TLAST;
wire DMAC_STR_IN_1_FLUSH, wire DMAC_STR_IN_1_FLUSH;
wire DMAC_ALLCH_STOP_REQ_NONSEC, wire DMAC_ALLCH_STOP_REQ_NONSEC;
wire DMAC_ALLCH_STOP_ACK_NONSEC, wire DMAC_ALLCH_STOP_ACK_NONSEC;
wire DMAC_ALLCH_PAUSE_REQ_NONSEC, wire DMAC_ALLCH_PAUSE_REQ_NONSEC;
wire DMAC_ALLCH_PAUSE_ACK_NONSEC, wire DMAC_ALLCH_PAUSE_ACK_NONSEC;
wire [2-1:0] DMAC_CH_ENABLED, wire [2-1:0] DMAC_CH_ENABLED;
wire [2-1:0] DMAC_CH_ERR, wire [2-1:0] DMAC_CH_ERR;
wire [2-1:0] DMAC_CH_STOPPED, wire [2-1:0] DMAC_CH_STOPPED;
wire [2-1:0] DMAC_CH_PAUSED, wire [2-1:0] DMAC_CH_PAUSED;
wire [2-1:0] DMAC_CH_PRIV, wire [2-1:0] DMAC_CH_PRIV;
wire DMAC_HALT_REQ, wire DMAC_HALT_REQ;
wire DMAC_RESTART_REQ, wire DMAC_RESTART_REQ;
wire DMAC_HALTED, wire DMAC_HALTED;
wire DMAC_BOOT_EN, wire DMAC_BOOT_EN;
wire [32-1:2] DMAC_BOOT_ADDR, wire [32-1:2] DMAC_BOOT_ADDR;
wire [ 7:0] DMAC_BOOT_MEMATTR, wire [ 7:0] DMAC_BOOT_MEMATTR;
wire [ 1:0] DMAC_BOOT_SHAREATTR wire [ 1:0] DMAC_BOOT_SHAREATTR;
// ------------------------------- // -------------------------------
// DMA Controller Instantiation // DMA Controller Instantiation
...@@ -191,38 +186,38 @@ ada_top_sldma350 u_dmac_0( ...@@ -191,38 +186,38 @@ ada_top_sldma350 u_dmac_0(
// Clock and Reset signals // Clock and Reset signals
.clk(HCLK), .clk(HCLK),
.resetn(HRESETn), .resetn(HRESETn),
.aclken_m0(DMAC_ACLKen), .aclken_m0(1'b1),
.pclken(PCLKEN), .pclken(PCLKEN),
// Q Channel signals // Q Channel signals
.clk_qreqn(DMAC_CLK_QREQN), .clk_qreqn(1'b1),
.clk_qacceptn(DMAC_CLK_QACCEPTN), .clk_qacceptn(DMAC_CLK_QACCEPTN),
.clk_qdeny(DMAC_CLK_QDENY), .clk_qdeny(DMAC_CLK_QDENY),
.clk_qactive(DMAC_CLK_QACTIVE), .clk_qactive(DMAC_CLK_QACTIVE),
// P Channel Signals // P Channel Signals
.preq(DMAC_PREQ), .preq(1'b0),
.pstate(DMAC_PSTATE), .pstate(4'b1000),
.paccept(DMAC_PACCEPT), .paccept(DMAC_PACCEPT),
.pdeny(DMAC_PDENY), .pdeny(DMAC_PDENY),
.pactive(DMAC_PACTIVE), .pactive(DMAC_PACTIVE),
.pwakeup(DMAC_PWAKEUP), .pwakeup(1'b1),
.pdebug(DMAC_PDEBUG), .pdebug(1'b0),
.psel(PSEL), .psel(PSEL),
.penable(PEN), .penable(PEN),
.pprot(DMAC_PPROT), .pprot(3'b100),
.pwrite(PWRITE), .pwrite(PWRITE),
.paddr(PADDR), .paddr(PADDR),
.pwdata(PWDATA), .pwdata(PWDATA),
.pstrb(DMAC_PSTRB), .pstrb(4'b1111),
.pready(DMAC_PREADY), .pready(PREADY),
.pslverr(DMAC_PSLVERR), .pslverr(PSLVERR),
.prdata(PRDATA), .prdata(PRDATA),
// AXI Write Channel Signals // AXI Write Channel Signals
.awakeup_m0(DMAC_AWAKEUP), .awakeup_m0(DMAC_AWAKEUP),
.awvalid_m0(DMAC_AWVALID), .awvalid_m0(DMAC_AWVALID),
.awaddr_m0(DMAC_AWADDR), .awaddr_m0(DMAC_AWADDR),
.awburst_m0(DMAC_AWBURST), .awburst_m0(DMAC_AWBURST),
.awid_m0(), .awid_m0(DMAC_AWID),
.awlen_m0(DMAC_AWLEN), .awlen_m0(DMAC_AWLEN),
.awsize_m0(DMAC_AWSIZE), .awsize_m0(DMAC_AWSIZE),
.awqos_m0(DMAC_AWQOS), .awqos_m0(DMAC_AWQOS),
...@@ -235,7 +230,7 @@ ada_top_sldma350 u_dmac_0( ...@@ -235,7 +230,7 @@ ada_top_sldma350 u_dmac_0(
.arvalid_m0(DMAC_ARVALID), .arvalid_m0(DMAC_ARVALID),
.araddr_m0(DMAC_ARADDR), .araddr_m0(DMAC_ARADDR),
.arburst_m0(DMAC_ARBURST), .arburst_m0(DMAC_ARBURST),
.arid_m0(), .arid_m0(DMAC_ARID),
.arlen_m0(DMAC_ARLEN), .arlen_m0(DMAC_ARLEN),
.arsize_m0(DMAC_ARSIZE), .arsize_m0(DMAC_ARSIZE),
.arqos_m0(DMAC_ARQOS), .arqos_m0(DMAC_ARQOS),
...@@ -253,15 +248,15 @@ ada_top_sldma350 u_dmac_0( ...@@ -253,15 +248,15 @@ ada_top_sldma350 u_dmac_0(
.wready_m0(DMAC_WREADY), .wready_m0(DMAC_WREADY),
// AXI Read Data Signals // AXI Read Data Signals
.rvalid_m0(DMAC_RVALID), .rvalid_m0(DMAC_RVALID),
.rid_m0(), .rid_m0(DMAC_RID),
.rlast_m0(DMAC_RLAST), .rlast_m0(DMAC_RLAST),
.rdata_m0(DMAC_RDATA), .rdata_m0(DMAC_RDATA),
.rpoison_m0(DMAC_RPOISON), .rpoison_m0(1'b0),
.rresp_m0(DMAC_RRESP), .rresp_m0(DMAC_RRESP),
.rready_m0(DMAC_RREADY), .rready_m0(DMAC_RREADY),
// AXI Write response signals // AXI Write response signals
.bvalid_m0(DMAC_BVALID), .bvalid_m0(DMAC_BVALID),
.bid_m0(), .bid_m0(DMAC_BID),
.bresp_m0(DMAC_BRESP), .bresp_m0(DMAC_BRESP),
.bready_m0(DMAC_BREADY), .bready_m0(DMAC_BREADY),
// Trigger 0 in // Trigger 0 in
...@@ -310,114 +305,130 @@ ada_top_sldma350 u_dmac_0( ...@@ -310,114 +305,130 @@ ada_top_sldma350 u_dmac_0(
.str_in_1_tlast(DMAC_STR_IN_1_TLAST), .str_in_1_tlast(DMAC_STR_IN_1_TLAST),
.str_in_1_flush(DMAC_STR_IN_1_FLUSH), .str_in_1_flush(DMAC_STR_IN_1_FLUSH),
.allch_stop_req_nonsec(DMAC_ALLCH_STOP_REQ_NONSEC), .allch_stop_req_nonsec(1'b0),
.allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC), .allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC),
.allch_pause_req_nonsec(DMAC_ALLCH_PAUSE_REQ_NONSEC), .allch_pause_req_nonsec(1'b0),
.allch_pause_ack_nonsec(DMAC_ALLCH_PAUSE_ACK_NONSEC), .allch_pause_ack_nonsec(DMAC_ALLCH_PAUSE_ACK_NONSEC),
.ch_enabled(DMAC_CH_ENABLED), .ch_enabled(DMAC_CH_ENABLED),
.ch_err(DMAC_CH_ERR), .ch_err(DMAC_CH_ERR),
.ch_stopped(DMAC_CH_STOPPED), .ch_stopped(DMAC_CH_STOPPED),
.ch_paused(DMAC_CH_PAUSED), .ch_paused(DMAC_CH_PAUSED),
.ch_priv(DMAC_CH_PRIV), .ch_priv(DMAC_CH_PRIV),
.halt_req(DMAC_HALT_REQ), .halt_req(1'b0),
.restart_req(DMAC_RESTART_REQ), .restart_req(1'b0),
.halted(DMAC_HALTED), .halted(DMAC_HALTED),
.boot_en(DMAC_BOOT_EN), .boot_en(1'b0),
.boot_addr(DMAC_BOOT_ADDR), .boot_addr(DMAC_BOOT_ADDR),
.boot_memattr(DMAC_BOOT_MEMATTR), .boot_memattr(DMAC_BOOT_MEMATTR),
.boot_shareattr(DMAC_BOOT_SHAREATTR) .boot_shareattr(DMAC_BOOT_SHAREATTR)
); );
xhb400 #(.DATA_WIDTH(SYS_DATA_W)) wire HTRANS_int;
wire HNONSEC_int;
assign HTRANS = HNONSEC_int ? 2'b10 : HTRANS_int;
xhb500_axi_to_ahb_bridge_sldma350 u_xhb
( (
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Clock and Reset // Clock and Reset
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
.CLK(HCLK), .clk(HCLK),
.nSYSRESET(HRESETn), .resetn(HRESETn),
.clk_qactive(),
.clk_qreqn(1'b1),
.clk_qacceptn(),
.clk_qdeny(),
.pwr_qactive(),
.pwr_qreqn(1'b1),
.pwr_qacceptn(),
.pwr_qdeny(),
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// AXI Master Interface // AXI Master Interface
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// Write Address Channel signals // Write Address Channel signals
.AWADDR(DMAC_AWADDR), .awvalid(DMAC_AWVALID),
.AWBURST(DMAC_AWBURST), .awready(DMAC_AWREADY),
.AWID(), .awaddr(DMAC_AWADDR),
.AWLEN(DMAC_AWLEN), .awburst(DMAC_AWBURST),
.AWSIZE(DMAC_AWSIZE), .awid(DMAC_AWID),
.AWLOCK(), .awlen(DMAC_AWLEN),
.AWPROT(DMAC_AWPROT), .awsize(DMAC_AWSIZE),
.AWCACHE(DMAC_AWCACHE), .awlock(1'b0),
.AWUSER(), .awprot(DMAC_AWPROT),
.AWSPARSE(), .awcache(DMAC_AWCACHE),
.AWVALID(DMAC_AWVALID),
.AWREADY(DMAC_AWREADY),
// Read Address Channel signals // Read Address Channel signals
.ARADDR(DMAC_ARADDR), .arvalid(DMAC_ARVALID),
.ARBURST(DMAC_ARBURST), .arready(DMAC_ARREADY),
.ARID(), .araddr(DMAC_ARADDR),
.ARLEN(DMAC_ARLEN), .arburst(DMAC_ARBURST),
.ARSIZE(DMAC_ARSIZE), .arid(DMAC_ARID),
.ARLOCK(), .arlen(DMAC_ARLEN),
.ARPROT(DMAC_ARPROT), .arsize(DMAC_ARSIZE),
.ARCACHE(DMAC_ARCACHE), .arlock(1'b0),
.ARUSER(), .arprot(DMAC_ARPROT),
.ARVALID(DMAC_ARVALID), .arcache(DMAC_ARCACHE),
.ARREADY(DMAC_ARREADY),
// Write Data Channel signals // Write Data Channel signals
.WLAST(DMAC_WLAST), .wvalid(DMAC_WVALID),
.WSTRB(DMAC_WSTRB), .wready(DMAC_WREADY),
.WDATA(DMAC_WDATA), .wlast(DMAC_WLAST),
.WUSER(), .wstrb(DMAC_WSTRB),
.WVALID(DMAC_WVALID), .wdata(DMAC_WDATA),
.WREADY(DMAC_WREADY),
// Read Data Channel signals // Read Data Channel signals
.RREADY(DMAC_RREADY), .rvalid(DMAC_RVALID),
.RVALID(DMAC_RVALID), .rready(DMAC_RREADY),
.RID(), .rid(DMAC_RID),
.RLAST(DMAC_RLAST), .rlast(DMAC_RLAST),
.RDATA(DMAC_RDATA), .rdata(DMAC_RDATA),
.RUSER(), .rresp(DMAC_RRESP),
.RRESP(DMAC_RRESP),
// Write Response Channel signals // Write Response Channel signals
.BREADY(DMAC_BREADY), .bready(DMAC_BREADY),
.BVALID(DMAC_BVALID), .bvalid(DMAC_BVALID),
.BID(), .bid(DMAC_BID),
.BRESP(DMAC_BRESP), .bresp(DMAC_BRESP),
.ardomain(DMAC_ARDOMAIN),
.awdomain(DMAC_AWDOMAIN),
.awakeup(DMAC_AWAKEUP),
.awnsaid(4'b0000),
.arnsaid(4'b0000),
.awqos(DMAC_AWQOS),
.arqos(DMAC_ARQOS),
.awregion(4'b0000),
.arregion(4'b0000),
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// AHB-Lite Slave Interface // AHB-Lite Slave Interface
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// AHB-Lite Master signals // AHB-Lite Master signals
.HTRANS(HTRANS), .hnonsec(HNONSEC_int),
.HBURST(HBURST), .haddr(HADDR),
.HADDR(HADDR), .htrans(HTRANS_int),
.HWRITE(HWRITE), .hsize(HSIZE),
.HSIZE(HSIZE), .hwrite(HWRITE),
.HWDATA(HWDATA), .hprot(HPROT),
.HPROT(HPROT), .hburst(HBURST),
.HMASTLOCK(HMASTLOCK), .hmastlock(HMASTLOCK),
.hwdata(HWDATA),
.hexcl(),
// AHB-Lite Slave Response signals // AHB-Lite Slave Response signals
.HREADY(HREADY), .hrdata(HRDATA),
.HRDATA(HRDATA), .hready(HREADY),
.HRESP(HRESP), .hresp(HRESP),
.hexokay(1'b0),
// Non-standard Exclusive Access signals
.EXREQ,
.EXRESP,
// Sideband AHB USER signals // Sideband AHB USER signals
.HAUSER, .hwstrb(),
.HWUSER, .hqos(),
.HRUSER .hregion(),
.hnsaid()
); );
endmodule endmodule
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