Add small configuration

config/cfg_dma_ahb.yaml

@@ -55,7 +55,7 @@ CHID_WIDTH: 0
 #
 #     Valid values:
 #         1-32
-GPO_WIDTH: 1
+GPO_WIDTH: 0
 
 #
 # CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
@@ -118,7 +118,7 @@ NUM_TRIGGER_IN: 2
 #
 #     Valid values:
 #         0-32
-NUM_TRIGGER_OUT: 2
+NUM_TRIGGER_OUT: 0
 
 #
 # TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in

config/cfg_dma_ahb_small.yaml

+#----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2021-2022 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#----------------------------------------------------------------------------
+#
+# Release Information : DMA350-r0p0-00rel0
+#
+# -----------------------------------------------------------------------------
+#  Abstract : User Configuration file for ADA DMA
+# -----------------------------------------------------------------------------
+
+#
+# CONFIG_NAME: Name of the configuration.
+#     Each unifiqued element and top is suffixed with
+#     _${CONFIG_NAME}
+#
+CONFIG_NAME: sldma350
+
+#
+# ADDR_WIDTH: Address Bus width
+#
+#     Valid values:
+#         32-64
+ADDR_WIDTH: 32
+
+#
+# DATA_WIDTH: Data Bus width
+#
+#     Valid values:
+#         [32,64,128]
+DATA_WIDTH: 32
+
+#
+# CHID_WIDTH: Width of the configurable channel ID user signal.
+#     When set to 0, then the archid and awchid ports are not present on the module.
+#
+#     Valid values:
+#         0-16
+CHID_WIDTH: 0
+
+#
+# GPO_WIDTH: Width of GPO output for every channel. When multiple channels have GPOs
+#     then the width must be set to the maximum number of GPOs a channel can have,
+#     and unused GPO ports need to be left unconnected. When all bits of CH_GPO_MASK
+#     is 0, this parameter is not relevant.
+#
+#     Valid values:
+#         1-32
+GPO_WIDTH: 0
+
+#
+# CH_GPO_MASK: A bitmask for enabling the GPO port for each channel. The width of the
+#     bitmask is NUM_CHANNELS-1. When bit n is set to 1 then the GPO is enabled for
+#     channel n and the gpo_ch_n[GPO_WIDTH-1:0] port appears on the module.
+#
+#     Valid values:
+#         0-(2^NUM_CHANNELS-1)
+CH_GPO_MASK: 0x0
+
+#
+# CH_STREAM_MASK: A bitmask for enabling the stream interfaces for each channel.
+#     The width of the bitmask is NUM_CHANNELS-1. When bit n is set to 1 then
+#     the stream interfaces are enabled for channel n and the relevant ports
+#     appears on the module. NOTE: When streaming interface is enabled the actual
+#     FIFO size of the channel will be the double of CH_<N>_FIFO_DEPTH
+#
+#     Valid values:
+#         0-(2^NUM_CHANNELS-1)
+CH_STREAM_MASK: 0x0
+
+#
+# CH_<N>_FIFO_DEPTH: Sets the FIFO depth for channel <N> that defines the number of
+#     DATA_WIDTH size entries a channel can hold for a transfer. N goes from 0 to
+#     NUM_CHANNELS-1. In combination with the TRANSIZE setting of the command, the
+#     FIFO depth defines the maximum burst size a channel can support. This setting
+#     needs to be aligned with the bandwidth requirements of the channel but it
+#     highly affects the area of the design.
+#
+#     Valid values:
+#         [1,2,4,8,16,32,64]
+CH_0_FIFO_DEPTH: 16
+CH_1_FIFO_DEPTH: 16
+
+#
+# CH_EXT_FEAT_MASK: A bitmask for enabling the extended feature set for each channel.
+#     The extension contains 2D, WRAP, TMPLT features. Default value enables it for
+#     the number of channels.
+#
+#     Valid values:
+#         0-(2^NUM_CHANNELS-1)
+CH_EXT_FEAT_MASK: 0x0
+
+#
+# NUM_CHANNELS: Number of configurable DMA channels.
+#
+#     Valid values:
+#         1-8
+NUM_CHANNELS: 2
+
+#
+# NUM_TRIGGER_IN: Number of trigger input ports.
+#
+#     Valid values:
+#         0-32
+NUM_TRIGGER_IN: 2
+
+#
+# NUM_TRIGGER_OUT: Number of trigger output ports.
+#
+#     Valid values:
+#         0-32
+NUM_TRIGGER_OUT: 0
+
+#
+# TRIG_IN_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger in
+#     interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_IN-1.
+#     When bit n is set to 1 then the trigger in interface is considered asynchronous
+#     and the synchronizer logic is placed on the selected input ports.
+#
+#     Valid values:
+#         0-(2^NUM_TRIGGER_IN-1)
+TRIG_IN_SYNC_EN_MASK: 0x0
+
+#
+# TRIG_OUT_SYNC_EN_MASK: A bitmask for enabling the synchronizers on the trigger out
+#     interfaces for each trigger port. The width of the bitmask is NUM_TRIGGER_OUT-1.
+#     When bit n is set to 1 then the trigger out interface is considered asynchronous
+#     and the synchronizer logic is placed on the selected input ports.
+#
+#     Valid values:
+#         0-(2^NUM_TRIGGER_OUT-1)
+TRIG_OUT_SYNC_EN_MASK: 0x0
+
+#
+# AXI5_M1_PRESENT: Enables an additional master port. When set the m1 master port is
+#     present on the top level port list and additional include file can be used with
+#     a System Verilog function that defines which address ranges are mapped to the m1
+#     interface.
+#
+#     Valid values:
+#         [0,1]
+AXI5_M1_PRESENT: 1
+
+#
+# SECEXT_PRESENT: Enables TrustZone security support.
+#
+#     Valid values:
+#         [0,1]
+SECEXT_PRESENT: 0
+
+#
+# AXI5_M1_ADDR_MAP: Select AXI M1 master.
+#
+#     Valid values:
+#         relative path to logical
+AXI5_M1_ADDR_MAP: models/modules/generic/address_map_m1_nanosoc.sv

flist/dma350_ahb_small_ip.flist

+//-----------------------------------------------------------------------------
+// MegaSoC DMA-350 Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Arm DMA-350
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// =============    DMA-350 search path    =============
++incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/
++incdir+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regmap_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_apb_regmap_conv_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_ro_ro_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_ro_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1c_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_w1s_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_reg_field_rw_rw_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_coreif_dmach_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_addrmap_dmach_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_interface_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_address_map_m1_sldma350_inc.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_flop_en/verilog/ada_flop_en.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_or_tree/verilog/ada_or_tree.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_gen_regif_dmainfo_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_flop.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_sync.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_mux2.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_or.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/models/cells/generic/ada_arm_idbit_v1.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/shared/verilog/ada_ecorevnum.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_top_sldma350/verilog/ada_top_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_read_switch_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_write_switch_wrapper_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_arbiter_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_qv_cmp_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_lrg_arb_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_grant_queue_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_full_f2s_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_biu_sldma350/verilog/ada_biu_reverse_s2f_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regif_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_regmap_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_fields_coreif_dmach_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_gen_coreif_res_dmach_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_fifo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_cmdlink_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_rd_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_wr_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_axi_stop_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_in_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_0_sldma350/verilog/ada_channel_0_trig_out_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regif_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_regmap_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_fields_coreif_dmach_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_gen_coreif_res_dmach_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_wr_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_1d_rd_ctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_fifo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_cmdlink_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_rd_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_wr_if_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_axi_stop_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_in_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_channel_1_sldma350/verilog/ada_channel_1_trig_out_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmainfo_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_coreif_dmansecctrl_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350_pkg.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regif_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_regmap_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_fields_coreif_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_gen_addrmap_dmansecctrl_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_apb_slave_mux_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmainfo_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_dmansecctrl_reg_bank_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigmask_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigin_used_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_trigout_used_sldma350.sv
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_ctrl_sldma350/verilog/ada_ctrl_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_qctrl_sldma350/verilog/ada_qctrl_sldma350.sv
+
+$(SOCLABS_SLDMA350_TECH_DIR)/src/logical/ada_trigmtx_sldma350/verilog/ada_trigmtx_sldma350.sv

makefile

@@ -42,6 +42,9 @@ config_dma_axi:
 config_dma_ahb:
 	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb.yaml --output ./src/
 	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb.cfg --output ./src/
+config_dma_ahb_small:
+	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/CG096-BU-50000-r0p0-00rel0/dma350/logical/generate --config ./config/cfg_dma_ahb_small.yaml --output ./src/
+	@$(ARM_IP_LIBRARY_PATH)/DMA-350/CG096-r0p0-00rel0/PL417-BU-50000-r0p1-00rel0/xhb500/logical/generate --config ./config/cfg_xhb_axi_to_ahb.cfg --output ./src/
 
 clean_ip:
 	@rm -rf ./src/*
\ No newline at end of file

wrapper/logical/sldma350_ahb.v

@@ -8,7 +8,7 @@
 //
 // Copyright 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
-
+`include "gen_defines.v"
 
 module sldma350_ahb #(
     parameter    SYS_ADDR_W  = 32,
@@ -57,7 +57,7 @@ module sldma350_ahb #(
     output wire   [SYS_DATA_W-1:0]  PRDATA,      // APB read data
     output wire                     PREADY,
     output wire                     PSLVERR,
-
+`ifdef DMA350_STREAM_2
     //  DMAC Channel 0 AXI stream out
     output wire                     DMAC_STR_OUT_0_TVALID,
     input  wire                     DMAC_STR_OUT_0_TREADY,
@@ -87,7 +87,7 @@ module sldma350_ahb #(
     input  wire [4-1:0]             DMAC_STR_IN_1_TSTRB,
     input  wire                     DMAC_STR_IN_1_TLAST,
     output wire                     DMAC_STR_IN_1_FLUSH,
-
+`endif
     // DMA Request and Status Port
     input  wire  [CHANNEL_NUM-1:0] DMA_REQ,     // DMA transfer request
     output wire  [CHANNEL_NUM-1:0] DMA_DONE,    // DMA transfer done
@@ -198,10 +198,6 @@ wire                     DMAC_TRIG_IN_1_REQ;
 wire  [1:0]              DMAC_TRIG_IN_1_REQ_TYPE;
 wire                     DMAC_TRIG_IN_1_ACK;
 wire [1:0]               DMAC_TRIG_IN_1_ACK_TYPE;
-wire                     DMAC_TRIG_OUT_0_REQ;
-wire                     DMAC_TRIG_OUT_0_ACK;
-wire                     DMAC_TRIG_OUT_1_REQ;
-wire                     DMAC_TRIG_OUT_1_ACK;
 wire [2-1:0]             DMAC_IRQ_CHANNEL;
 wire                     DMAC_IRQ_COMB_NONSEC;
 
@@ -365,15 +361,10 @@ ada_top_sldma350 u_dmac_0(
     .trig_in_1_req_type(DMAC_TRIG_IN_1_REQ_TYPE),
     .trig_in_1_ack(DMAC_TRIG_IN_1_ACK),
     .trig_in_1_ack_type(DMAC_TRIG_IN_1_ACK_TYPE),
-    // Trigger 0 out
-    .trig_out_0_req(DMAC_TRIG_OUT_0_REQ),
-    .trig_out_0_ack(DMAC_TRIG_OUT_0_ACK),
-    // Trigger 1 out
-    .trig_out_1_req(DMAC_TRIG_OUT_1_REQ),
-    .trig_out_1_ack(DMAC_TRIG_OUT_1_ACK),
     // Interrupt Signals
     .irq_channel(DMA_DONE),
     .irq_comb_nonsec(DMAC_IRQ_COMB_NONSEC),
+`ifdef DMA350_STREAM_2
     // AXI Stream 0 out
     .str_out_0_tvalid(DMAC_STR_OUT_0_TVALID),
     .str_out_0_tready(DMAC_STR_OUT_0_TREADY),
@@ -400,6 +391,7 @@ ada_top_sldma350 u_dmac_0(
     .str_in_1_tstrb(DMAC_STR_IN_1_TSTRB),
     .str_in_1_tlast(DMAC_STR_IN_1_TLAST),
     .str_in_1_flush(DMAC_STR_IN_1_FLUSH),
+`endif
 
     .allch_stop_req_nonsec(1'b0),
     .allch_stop_ack_nonsec(DMAC_ALLCH_STOP_ACK_NONSEC),
@@ -635,11 +627,8 @@ sldma350_trig_converter u_trig_conv_0 (
     .trig_in_req_type(DMAC_TRIG_IN_0_REQ_TYPE),
     .trig_in_ack(DMAC_TRIG_IN_0_ACK),
     .trig_in_ack_type(DMAC_TRIG_IN_0_ACK_TYPE),
-    .trig_out_req(DMAC_TRIG_OUT_0_REQ),
-    .trig_out_ack(DMAC_TRIG_OUT_0_ACK),
     .DMAC_DMA_REQ(DMA_REQ[0]),
-    .DMAC_DMA_REQ_ERR(),
-    .DMAC_DMA_DONE()
+    .DMAC_DMA_REQ_ERR()
 );
 
 sldma350_trig_converter u_trig_conv_1 (
@@ -649,11 +638,8 @@ sldma350_trig_converter u_trig_conv_1 (
     .trig_in_req_type(DMAC_TRIG_IN_1_REQ_TYPE),
     .trig_in_ack(DMAC_TRIG_IN_1_ACK),
     .trig_in_ack_type(DMAC_TRIG_IN_1_ACK_TYPE),
-    .trig_out_req(DMAC_TRIG_OUT_1_REQ),
-    .trig_out_ack(DMAC_TRIG_OUT_1_ACK),
     .DMAC_DMA_REQ(DMA_REQ[1]),
-    .DMAC_DMA_REQ_ERR(),
-    .DMAC_DMA_DONE()
+    .DMAC_DMA_REQ_ERR()
 );
 
 endmodule

wrapper/logical/sldma350_trig_converter.v

@@ -16,18 +16,14 @@ module sldma350_trig_converter (
     output wire [1:0]   trig_in_req_type,
     input  wire         trig_in_ack,
     input  wire [1:0]   trig_in_ack_type,
-    input  wire         trig_out_req,
-    output wire         trig_out_ack,
     input  wire         DMAC_DMA_REQ,
-    output wire         DMAC_DMA_REQ_ERR,
-    output wire         DMAC_DMA_DONE
+    output wire         DMAC_DMA_REQ_ERR
 );
 
  parameter IDLE  = 2'b00,START_REQ = 2'b01,ERROR = 2'b10,END_REQ = 2'b11;
 
 reg [1:0]  state;
 reg        dma_err;
-reg        out_ack;
 reg        req_err;
 reg [1:0]  next_state;
 reg        trig_req;
@@ -35,23 +31,16 @@ reg        trig_req;
 assign trig_in_req = trig_req;
 assign DMAC_DMA_REQ_ERR = dma_err;
 assign trig_in_req_type = 2'b10;
-assign DMAC_DMA_DONE = out_ack;
 
 always @(posedge clk or negedge resetn) begin
     if(~resetn) begin
         state <= IDLE;
         dma_err<= 1'b0;
-        out_ack <= 1'b0;
     end else begin
         state <= next_state;
         if (req_err) begin
         dma_err <= 1'b1;
         end
-        if (trig_out_req) begin
-            out_ack <= 1'b1;
-        end else begin
-            out_ack <= 1'b0;
-        end
     end
     
 end