Clean Lint of SLCore M0

flist/cortexm0_ip.flist

@@ -16,11 +16,7 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
 -incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
--incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
--incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
--incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
 -incdir $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
 
 // Cortex-M0 Core IP

hal/slcorem0_ip.waive

@@ -18,12 +18,24 @@ lint_checking designunit = slcorem0
     DIFCLK {"SYS_|CORE_"} off;
     DIFRST {"SYS_|CORE_"} off;
     
+    // System HCLK is Alias of System FClk
+    IOCOMB {"SYS_HCLK"} off;
+    
+    // Acts as a wrapper - some outputs are not registered (registered at lower levels)
+    TPOUNR off;
+    
+    // Following Intergation Output Signals are Unused
+    UNCONN {"HMASTER|TDO|nTDOEN|DBGRESTARTED|HALTED|WICSENSE|CODEHINTDE|SPECHTRANS|CODENSEQ"} off;
+    UNCONO {"HMASTER|TDO|nTDOEN|DBGRESTARTED|HALTED|WICSENSE|CODEHINTDE|SPECHTRANS|CODENSEQ"} off;
 }
 
 lint_checking designunit = slcorem0_integration
 {
     // Constant Conditional for Debug Configuration
     CONSTC {"cfg_dbg"} off;
+    
+    // lowercase n used to represent negation in signal name
+    UCCONN {"n"} off;
 }
 
 lint_checking designunit = slcorem0_prmu
@@ -31,7 +43,26 @@ lint_checking designunit = slcorem0_prmu
     // Constant Conditional for Clock Gating
     CONSTC {"CLKGATE"} off;
     
-    // With CLock Gating Disabled, Clocks may be aliased
+    // With Clock Gating Disabled, Clocks may be aliased and Some Output may not be used
     DALIAS {"CLK"} off;
     DIFCLK {"CLKGATE"} off;
+    // Some PMU Output Signals are Unused
+    UNCONO {"HCLK|DCLK|SCLK|SYSISOLATEn|SYSRETAINn|DBGISOLATEn"} off;
+    // System HClock is generated from FClock and needs to be always on
+    FDTHRU {"CLKGATE|SYS_HCLK"} off;
+    
+    // Output Signals SYSISOLATEn, SYSRETAINn, DBGISOLATEn are Unused
+    UNCONN {"SYSISOLATEn|SYSRETAINn|DBGISOLATEn"} off;
+}
+
+lint_checking designunit = slcorem0_stclkctrl
+{
+    // Bit-wise Inversion for Reset (Arm implemented)
+    LOGNEG {"RESET"} off;
+    
+    // Arm Don't Like to use begin and end in if statements (not going to change their IP)
+    NBGEND off;
+    
+    // STCALIB output is Assigned to a Constant Value
+    TIELOG {"STCALIB"} off;
 }

src/verilog/slcorem0.v

@@ -161,11 +161,6 @@ module slcorem0 #(
   // -------------------------------
   // Cortex-M0 CPU Instantiation
   // -------------------------------
-  // Processor status
-  wire      [2:0]   CORE_CODEHINTDE;
-  wire              CORE_SPECHTRANS;
-  wire              CORE_CODENSEQ;
-  wire              CORE_SHAREABLE;
   
   // Cortex-M0 Logic Instantiation
   slcorem0_integration #(
@@ -223,9 +218,9 @@ module slcorem0 #(
     .HRESP         (HRESP),
     .HMASTER       ( ),
 
-    .CODEHINTDE    (CORE_CODEHINTDE),
-    .SPECHTRANS    (CORE_SPECHTRANS),
-    .CODENSEQ      (CORE_CODENSEQ),
+    .CODEHINTDE    ( ),
+    .SPECHTRANS    ( ),
+    .CODENSEQ      ( ),
 
     // Interrupts
     .IRQ           (CORE_IRQ[31:0]),

src/verilog/slcorem0_stclkctrl.v

@@ -56,7 +56,7 @@ module slcorem0_stclkctrl #(
   assign STCALIB[23:0] = {24{1'b0}}; // 10 ms value  set to 0, indicate this value is not used
 
   // Divider
-  wire [17:0] reg_clk_div_min1 = reg_clk_divider - 1;
+  wire [17:0] reg_clk_div_min1 = reg_clk_divider - 18'd1;
   always @(posedge FCLK or negedge SYSRESETn)
   begin
   if (~SYSRESETn)