Changed Table Base Address Defaults

src/verilog/slcorem0.v

@@ -23,7 +23,7 @@ module slcorem0 #(
   parameter        WPT              = 2,   // Number of DWT comparators
   parameter        RESET_ALL_REGS   = 0,   // Do not reset all registers
   parameter        INCLUDE_JTAG     = 0,    // Do not Include JTAG feature
-  parameter [31:0] ROMTABLE_BASE    = 32'hE00FF003 // Defaultly Points to Core ROM Table
+  parameter [31:0] ROMTABLE_BASE    = 32'hE00FF000 // Defaultly Points to Core ROM Table
 )(
   // System Input Clocks and Resets
   input  wire          SYS_FCLK,              // Free running clock

src/verilog/slcorem0_integration.v

@@ -95,7 +95,7 @@ module slcorem0_integration
                                   //   1 = one
                                   //   2 = two
     // ----------------------------------------------------------------------
-    parameter [31:0] ROMTABLE_BASE = 32'hE00FF003) // ROM Table Base Address
+    parameter [31:0] ROMTABLE_BASE = 32'hE00FF000) // ROM Table Base Address
                                 // - Defaultly points to Core ROMTABLE
     // ----------------------------------------------------------------------
 
@@ -379,7 +379,7 @@ module slcorem0_integration
           .SLVRDATA                       (slv_rdata_dap[31:0]),
           .SLVREADY                       (slv_ready_dap),
           .SLVRESP                        (slv_resp_dap),
-          .BASEADDR                       (ROMTABLE_BASE),
+          .BASEADDR                       (ROMTABLE_BASE + 32'h00000003),
           .ECOREVNUM                      (ECOREVNUM[27:20]),
           .SE                             (SE)
           );