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SoCLabs
SLCore-M0 Tech
Commits
26e44cde
Commit
26e44cde
authored
2 years ago
by
dam1n19
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Updated lint flow
parent
b5948804
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3 changed files
flist/slcorem0.flist
+3
-3
3 additions, 3 deletions
flist/slcorem0.flist
hal/cortexm0_ip.bb
+7
-7
7 additions, 7 deletions
hal/cortexm0_ip.bb
makefile
+13
-3
13 additions, 3 deletions
makefile
with
23 additions
and
13 deletions
flist/slcorem0.flist
+
3
−
3
View file @
26e44cde
...
...
@@ -12,8 +12,8 @@
// Abstract : Verilog Command File for SLCore-M0 IP
//-----------------------------------------------------------------------------
// SLCore IP
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist
// Include Cortex-M0 IP
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/cortexm0_ip.flist
// SLCore IP
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_ip.flist
This diff is collapsed.
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hal/cortexm0_ip.bb
+
7
−
7
View file @
26e44cde
...
...
@@ -16,30 +16,30 @@ bb_list
{
// Exclude Cortex M0 Debug Reset Synchroniser as Arm IP
designunit = cm0_dbg_reset_sync;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/models/cells/cm0_dbg_reset_sync.v;
file = $ARM_
CORTEX_M0_DIR
/models/cells/cm0_dbg_reset_sync.v;
// Exclude Cortex M0 as Arm IP
designunit = CORTEXM0;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/cortexm0/verilog/CORTEXM0.v;
file = $ARM_
CORTEX_M0_DIR
/cortexm0/verilog/CORTEXM0.v;
// Exclude Cortex M0 Debug Access Port as Arm IP
designunit = CORTEXM0DAP;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/cortexm0_dap/verilog/CORTEXM0DAP.v;
file = $ARM_
CORTEX_M0_DIR
/cortexm0_dap/verilog/CORTEXM0DAP.v;
// Exclude Cortex M0 Wake on Interrupt Controller as Arm IP
designunit = cortexm0_wic;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/cortexm0_integration/verilog/cortexm0_wic.v;
file = $ARM_
CORTEX_M0_DIR
/cortexm0_integration/verilog/cortexm0_wic.v;
// Exclude Cortex M0 Reset Send Set as Arm IP
designunit = cm0_rst_send_set;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/models/cells/cm0_rst_send_set.v;
file = $ARM_
CORTEX_M0_DIR
/models/cells/cm0_rst_send_set.v;
// Exclude Cortex M0 Reset Synchroniser as Arm IP
designunit = cm0_rst_sync;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/models/cells/cm0_rst_sync.v;
file = $ARM_
CORTEX_M0_DIR
/models/cells/cm0_rst_sync.v;
// Exclude Cortex M0 PMU as Arm IP
designunit = cortexm0_pmu;
file = $ARM_
IP_LIBRARY_PATH/latest/Cortex-M0/logical
/cortexm0_integration/verilog/cortexm0_pmu.v;
file = $ARM_
CORTEX_M0_DIR
/cortexm0_integration/verilog/cortexm0_pmu.v;
}
\ No newline at end of file
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makefile
+
13
−
3
View file @
26e44cde
...
...
@@ -11,12 +11,22 @@
include
$(SOCLABS_SOCTOOLS_FLOW_DIR)/resources/hal/makefile.hal_checks
QUICKSTART
?=
no
# System Design Filelist
ifeq
($(QUICKSTART),yes)
ARM_CORTEX_M0_DIR
?=
$(
ARM_IP_LIBRARY_PATH
)
/latest/Cortex-M0-QS/Cortex-M0-logical
DESIGN_VC
?=
$(
SOCLABS_SLCOREM0_TECH_DIR
)
/flist/slcorem0_qs.flist
else
ARM_CORTEX_M0_DIR
?=
$(
ARM_IP_LIBRARY_PATH
)
/latest/Cortex-M0/logical
DESIGN_VC
?=
$(
SOCLABS_SLCOREM0_TECH_DIR
)
/flist/slcorem0.flist
endif
export
ARM_CORTEX_M0_DIR
LINT_DIR
=
$(
SOCLABS_PROJECT_DIR
)
/lint/slcorem0
LINT_INFO_DIR
=
$(
SOCLABS_SLCOREM0_TECH_DIR
)
/hal
# Core Design Filelist
DESIGN_VC
?=
$(
SOCLABS_SLCOREM0_TECH_DIR
)
/flist/slcorem0_ip.flist
# Defines
DEFINES_VC
+=
$(
MEM_INIT
)
+define+CORTEX_M0 +define+USE_TARMAC
...
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