Updated filelist

flist/slcorem0.flist

@@ -15,8 +15,23 @@
 // ============= Verilog library extensions ===========
 +libext+.v+.vlib
 
-// =============    NanoSoC Bus Matrix IP search path    =============
+// =============    SLCore M0 IP search path    =============
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_prmu.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_stclkctrl.v
 $(SOCLABS_SLCOREM0_TECH_DIR)/src/verilog/slcorem0_rstctrl.v
+
+// =============    Cortex M0 IP search path    =============
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
+-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog
+
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_dap/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/cortexm0_integration/verilog
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/cells
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/models/wrappers
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical/ualdis/verilog