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Commit dd4d87f0 authored by dam1n19's avatar dam1n19
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design: ATO2-24: Added last signal to FIFO and added lint to flow

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#-----------------------------------------------------------------------------
# SoC Labs socsim script to run linting
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright 2022, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#!/usr/bin/env bash
verilator --lint-only $*
\ No newline at end of file
File moved
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......@@ -17,26 +17,29 @@ module vr_fifo #(
input logic nrst,
input logic en,
// Synchronous, localised reset
input logic sync_rst,
// In (Write) Control
input logic [DATA_W-1:0] in_data,
input logic in_last,
input logic in_valid,
output logic in_ready,
// Out (Read) Control
output logic [DATA_W-1:0] out_data,
output logic out_last,
input logic out_ready,
output logic out_valid
);
assign out_data = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
logic in_shake; // Successful Write Handshake
logic out_shake; // Successful Read Handshake
assign in_shake = (in_valid == 1'b1) && (in_ready == 1'b1);
assign out_shake = (out_valid == 1'b1) && (out_ready == 1'b1);
logic [DATA_W-1:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
logic [DATA_W:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
......@@ -56,8 +59,10 @@ module vr_fifo #(
// WriteValid: WritePtr - ReadPtr < 3'd4
// ReadValid: WritePtr - ReadPtr - 1 < 3'd4
assign {out_data,out_last} = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
always_ff @(posedge clk, negedge nrst) begin
if (!nrst) begin
if ((!nrst) || sync_rst) begin
// Under Reset
// - Pointers reset to 0 (FIFO is empty without needing to reset the memories)
// - Control taken low
......@@ -72,7 +77,7 @@ module vr_fifo #(
// Empty Rows in FIFO in FIFO
if (in_shake) begin
// Successful Handshake store data in FIFO and increment Write Pointer
fifo [write_ptr[PTR_W-2:0]] <= in_data;
fifo [write_ptr[PTR_W-2:0]] <= {in_data,in_last};
write_ptr <= write_ptr + 1;
if ((ptr_dif + (1 - out_shake)) < DEPTH) begin
// Still space in FIFO after latest write
......
......@@ -14,8 +14,8 @@
# Set environment Variables for Repository
export SHA_2_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
# Add simulation directory to Path
export PATH=$PATH:$SHA_2_ACC_DIR/simulate
# Add flow directory to Path
export PATH=$PATH:$SHA_2_ACC_DIR/flow
# Set Default Simulator
export SIMULATOR="ivlog"
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