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SoCLabs
SoCLabs SHA-2 Accelerator
Commits
b34860b7
Commit
b34860b7
authored
2 years ago
by
dam1n19
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Continued work on hashing algorithm
parent
7e14ebac
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3 changed files
hdl/src/hash_process.sv
+351
-8
351 additions, 8 deletions
hdl/src/hash_process.sv
hdl/src/sha_2_pkg.sv
+95
-93
95 additions, 93 deletions
hdl/src/sha_2_pkg.sv
hdl/verif/tb_hash_process.sv
+21
-9
21 additions, 9 deletions
hdl/verif/tb_hash_process.sv
with
467 additions
and
110 deletions
hdl/src/hash_process.sv
+
351
−
8
View file @
b34860b7
...
...
@@ -8,6 +8,9 @@
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include
"sha_2_pkg.sv"
module
hash_process
(
input
logic
clk
,
input
logic
nrst
,
...
...
@@ -29,14 +32,354 @@ module hash_process (
input
logic
data_out_ready
);
// Message Chunks
logic
[
31
:
0
]
M
[
15
:
0
];
import
sha_2_pkg
::*
;
genvar
i
;
generate
for
(
i
=
0
;
i
<
16
;
i
++
)
begin
assign
M
[
i
]
=
data_in
[(
16
*
i
)
-
1
:
16
*
(
i
-
1
)];
end
endgenerate
// Message Chunks
logic
[
31
:
0
]
M
[
15
:
0
];
// Assign M Variables to 32 bit chunks of the input data
genvar
i
;
generate
for
(
i
=
0
;
i
<
16
;
i
++
)
begin
assign
M
[
i
]
=
data_in
[(
32
*
(
i
+
1
))
-
1
:
32
*
i
];
end
endgenerate
// Hash Value Registers
logic
[
31
:
0
]
H
[
7
:
0
];
logic
[
31
:
0
]
next_H
[
7
:
0
];
// Message Schedule Registers
logic
[
31
:
0
]
W
[
63
:
0
];
logic
[
31
:
0
]
next_W
[
63
:
0
];
// Working Registers
logic
[
31
:
0
]
a
,
b
,
c
,
d
,
e
,
f
,
g
,
h
;
logic
[
31
:
0
]
next_a
,
next_b
,
next_c
,
next_d
,
next_e
,
next_f
,
next_g
,
next_h
;
logic
[
31
:
0
]
T1
,
T2
;
logic
[
31
:
0
]
next_T1
,
next_T2
;
// State Machine Registers
logic
[
2
:
0
]
state
,
next_state
;
logic
[
511
:
0
]
next_data_out
;
logic
next_data_in_ready
,
next_data_out_valid
,
next_data_out_last
;
logic
[
5
:
0
]
hash_iter
,
next_hash_iter
;
logic
last_block
,
next_last_block
;
// // SHA-2 Constants
logic
[
31
:
0
]
K
[
63
:
0
];
assign
K
[
0
]
=
32'h428a2f98
;
assign
K
[
1
]
=
32'h71374491
;
assign
K
[
2
]
=
32'hb5c0fbcf
;
assign
K
[
3
]
=
32'he9b5dba5
;
assign
K
[
4
]
=
32'h3956c25b
;
assign
K
[
5
]
=
32'h59f111f1
;
assign
K
[
6
]
=
32'h923f82a4
;
assign
K
[
7
]
=
32'hab1c5ed5
;
assign
K
[
8
]
=
32'hd807aa98
;
assign
K
[
9
]
=
32'h12835b01
;
assign
K
[
10
]
=
32'h243185be
;
assign
K
[
11
]
=
32'h550c7dc3
;
assign
K
[
12
]
=
32'h72be5d74
;
assign
K
[
13
]
=
32'h80deb1fe
;
assign
K
[
14
]
=
32'h9bdc06a7
;
assign
K
[
15
]
=
32'hc19bf174
;
assign
K
[
16
]
=
32'he49b69c1
;
assign
K
[
17
]
=
32'hefbe4786
;
assign
K
[
18
]
=
32'h0fc19dc6
;
assign
K
[
19
]
=
32'h240ca1cc
;
assign
K
[
20
]
=
32'h2de92c6f
;
assign
K
[
21
]
=
32'h4a7484aa
;
assign
K
[
22
]
=
32'h5cb0a9dc
;
assign
K
[
23
]
=
32'h76f988da
;
assign
K
[
24
]
=
32'h983e5152
;
assign
K
[
25
]
=
32'ha831c66d
;
assign
K
[
26
]
=
32'hb00327c8
;
assign
K
[
27
]
=
32'hbf597fc7
;
assign
K
[
28
]
=
32'hc6e00bf3
;
assign
K
[
29
]
=
32'hd5a79147
;
assign
K
[
30
]
=
32'h06ca6351
;
assign
K
[
31
]
=
32'h14292967
;
assign
K
[
32
]
=
32'h27b70a85
;
assign
K
[
33
]
=
32'h2e1b2138
;
assign
K
[
34
]
=
32'h4d2c6dfc
;
assign
K
[
35
]
=
32'h53380d13
;
assign
K
[
36
]
=
32'h650a7354
;
assign
K
[
37
]
=
32'h766a0abb
;
assign
K
[
38
]
=
32'h81c2c92e
;
assign
K
[
39
]
=
32'h92722c85
;
assign
K
[
40
]
=
32'ha2bfe8a1
;
assign
K
[
41
]
=
32'ha81a664b
;
assign
K
[
42
]
=
32'hc24b8b70
;
assign
K
[
43
]
=
32'hc76c51a3
;
assign
K
[
44
]
=
32'hd192e819
;
assign
K
[
45
]
=
32'hd6990624
;
assign
K
[
46
]
=
32'hf40e3585
;
assign
K
[
47
]
=
32'h106aa070
;
assign
K
[
48
]
=
32'h19a4c116
;
assign
K
[
49
]
=
32'h1e376c08
;
assign
K
[
50
]
=
32'h2748774c
;
assign
K
[
51
]
=
32'h34b0bcb5
;
assign
K
[
52
]
=
32'h391c0cb3
;
assign
K
[
53
]
=
32'h4ed8aa4a
;
assign
K
[
54
]
=
32'h5b9cca4f
;
assign
K
[
55
]
=
32'h682e6ff3
;
assign
K
[
56
]
=
32'h748f82ee
;
assign
K
[
57
]
=
32'h78a5636f
;
assign
K
[
58
]
=
32'h84c87814
;
assign
K
[
59
]
=
32'h8cc70208
;
assign
K
[
60
]
=
32'h90befffa
;
assign
K
[
61
]
=
32'ha4506ceb
;
assign
K
[
62
]
=
32'hbef9a3f7
;
assign
K
[
63
]
=
32'hc67178f2
;
// ssig1 next_W assignments - issues using functions with arrayed objects in ivlog
logic
[
31
:
0
]
ssig1_next_W
[
63
:
0
];
generate
for
(
i
=
0
;
i
<
64
;
i
++
)
begin
assign
ssig1_next_W
[
i
]
=
((
next_W
[
i
]
<<
15
)
|
(
next_W
[
i
]
>>
17
))
^
((
next_W
[
i
]
<<
13
)
|
(
next_W
[
i
]
>>
19
))
^
(
next_W
[
i
]
>>
10
);
end
endgenerate
// State Machine Sequential Logic
always_ff
@
(
posedge
clk
,
negedge
nrst
)
begin
if
((
!
nrst
)
|
sync_rst
)
begin
state
<=
3'd0
;
hash_iter
<=
6'd0
;
last_block
<=
1'b0
;
data_in_ready
<=
1'b0
;
data_out_valid
<=
1'b0
;
data_out_last
<=
1'b0
;
data_out
<=
512'd0
;
// Reset Working Registers
a
<=
32'd0
;
b
<=
32'd0
;
c
<=
32'd0
;
d
<=
32'd0
;
e
<=
32'd0
;
f
<=
32'd0
;
g
<=
32'd0
;
h
<=
32'd0
;
// Reset H Registers
for
(
int
i
=
0
;
i
<
8
;
i
++
)
begin
H
[
i
]
<=
32'd0
;
end
// Reset W Registers
for
(
int
i
=
0
;
i
<
64
;
i
++
)
begin
W
[
i
]
<=
32'd0
;
end
// Reset Temporary Registers
T1
<=
32'd0
;
T2
<=
32'd0
;
end
else
begin
state
<=
next_state
;
hash_iter
<=
next_hash_iter
;
last_block
<=
next_last_block
;
data_in_ready
<=
next_data_in_ready
;
data_out_valid
<=
next_data_out_valid
;
data_out_last
<=
next_data_out_last
;
data_out
<=
next_data_out
;
// Set Working Registers
a
<=
next_a
;
b
<=
next_b
;
c
<=
next_c
;
d
<=
next_d
;
e
<=
next_e
;
f
<=
next_f
;
g
<=
next_g
;
h
<=
next_h
;
// Set H Registers
for
(
int
i
=
0
;
i
<
8
;
i
++
)
begin
H
[
i
]
<=
next_H
[
i
];
end
// Set W Registers
for
(
int
i
=
0
;
i
<
64
;
i
++
)
begin
W
[
i
]
<=
next_W
[
i
];
end
// Set Temporary Registers
T1
<=
next_T1
;
T2
<=
next_T2
;
end
end
// State Machine Combinatorial Logic
always_comb
begin
// Default
next_state
=
state
;
next_hash_iter
=
hash_iter
;
next_last_block
=
last_block
;
next_data_in_ready
=
data_in_ready
;
next_data_out_valid
=
data_out_valid
;
next_data_out_last
=
data_out_last
;
next_data_out
=
data_out
;
// Set next Working Registers
next_a
=
a
;
next_b
=
b
;
next_c
=
c
;
next_d
=
d
;
next_e
=
e
;
next_f
=
f
;
next_g
=
g
;
next_h
=
h
;
// Set next H Registers
for
(
int
i
=
0
;
i
<
8
;
i
++
)
begin
next_H
[
i
]
=
H
[
i
];
end
// Set next W Registers
for
(
int
i
=
0
;
i
<
64
;
i
++
)
begin
next_W
[
i
]
=
W
[
i
];
end
// Set Temporary Registers
next_T1
=
T1
;
next_T2
=
T2
;
// Override
case
(
state
)
3'd0
:
begin
// Initialise Hash Registers -- this state may be able to be removed (reset values could be changed to these values)
if
(
!
(
data_out_valid
&&
!
data_out_ready
))
begin
// If data out handshake has been seen, drop valid
next_data_out_valid
=
1'b0
;
end
// Initialise Hash Value Registers
next_H
[
0
]
=
32'h6a09e667
;
next_H
[
1
]
=
32'hbb67ae85
;
next_H
[
2
]
=
32'h3c6ef372
;
next_H
[
3
]
=
32'ha54ff53a
;
next_H
[
4
]
=
32'h510e527f
;
next_H
[
5
]
=
32'h9b05688c
;
next_H
[
6
]
=
32'h1f83d9ab
;
next_H
[
7
]
=
32'h5be0cd19
;
next_data_in_ready
=
1'b1
;
next_state
=
3'd1
;
end
3'd1
:
begin
// Perform Hash Initialisation
if
(
!
(
data_out_valid
&&
!
data_out_ready
))
begin
// If data out handshake has been seen, drop valid
next_data_out_valid
=
1'b0
;
end
if
(
data_in_valid
&&
data_in_ready
)
begin
// Valid Handshake and data can be processed
// Use the Message chunks to populate the message schedule
for
(
logic
[
31
:
0
]
t
=
0
;
t
<
16
;
t
++
)
begin
next_W
[
t
]
=
M
[
t
];
end
for
(
logic
[
31
:
0
]
t
=
16
;
t
<
64
;
t
++
)
begin
next_W
[
t
]
=
ssig1_next_W
[
t
-
2
]
+
next_W
[
t
-
32'd7
]
+
ssig0
(
t
-
15
)
+
next_W
[
t
-
32'd16
];
// next_W[t] = next_W[t-32'd7] + ssig0(t-15) + next_W[t-32'd16];
end
// Set Working Variables
next_a
=
H
[
0
];
next_b
=
H
[
1
];
next_c
=
H
[
2
];
next_d
=
H
[
3
];
next_e
=
H
[
4
];
next_f
=
H
[
5
];
next_g
=
H
[
6
];
next_h
=
H
[
7
];
// Move to next state
next_state
=
3'd2
;
next_hash_iter
=
6'd0
;
next_last_block
=
data_in_last
;
// Drop Ready Signal to confirm handshake
next_data_in_ready
=
1'b0
;
end
end
3'd2
:
begin
// Perform the main hash computation
if
(
!
(
data_out_valid
&&
!
data_out_ready
))
begin
// If data out handshake has been seen, drop valid
next_data_out_valid
=
1'b0
;
end
// Perform Hash Function
next_T1
=
h
+
bsig1
(
e
)
+
ch
(
e
,
f
,
g
)
+
K
[
hash_iter
]
+
W
[
hash_iter
];
next_T2
=
bsig0
(
a
)
+
maj
(
a
,
b
,
c
);;
next_a
=
T1
+
T2
;
next_b
=
a
;
next_c
=
b
;
next_d
=
c
;
next_e
=
d
+
T1
;
next_f
=
e
;
next_g
=
f
;
next_h
=
g
;
// Decrement Iteration Register
next_hash_iter
=
hash_iter
+
6'd1
;
if
(
hash_iter
==
63
)
begin
next_state
=
3'd3
;
end
end
3'd3
:
begin
// Compute intermediate hash value
if
(
!
(
data_out_valid
&&
!
data_out_ready
))
begin
// If data out handshake has been seen, drop valid
next_data_out_valid
=
1'b0
;
end
next_H
[
0
]
=
a
+
H
[
0
];
next_H
[
1
]
=
b
+
H
[
1
];
next_H
[
2
]
=
c
+
H
[
2
];
next_H
[
3
]
=
d
+
H
[
3
];
next_H
[
4
]
=
e
+
H
[
4
];
next_H
[
5
]
=
f
+
H
[
5
];
next_H
[
6
]
=
g
+
H
[
6
];
next_H
[
7
]
=
h
+
H
[
7
];
if
(
last_block
)
begin
if
(
!
data_out_valid
)
begin
// No Data waiting at output
next_data_out
=
{
next_H
[
7
],
next_H
[
6
],
next_H
[
5
],
next_H
[
4
],
next_H
[
3
],
next_H
[
2
],
next_H
[
1
],
next_H
[
0
]
}
;
next_data_out_last
=
1'b1
;
next_data_out_valid
=
1'b1
;
// Next State Logic
next_state
=
3'd1
;
next_data_in_ready
=
1'b1
;
// Initialise Hash Value Registers
next_H
[
0
]
=
32'h6a09e667
;
next_H
[
1
]
=
32'hbb67ae85
;
next_H
[
2
]
=
32'h3c6ef372
;
next_H
[
3
]
=
32'ha54ff53a
;
next_H
[
4
]
=
32'h510e527f
;
next_H
[
5
]
=
32'h9b05688c
;
next_H
[
6
]
=
32'h1f83d9ab
;
next_H
[
7
]
=
32'h5be0cd19
;
end
else
begin
// Still Waiting for previous data to be recieved
next_state
=
3'd4
;
next_data_in_ready
=
1'b0
;
end
end
else
begin
// Next State Logic
next_data_in_ready
=
1'b1
;
next_state
=
3'd1
;
end
end
3'd4
:
begin
// Output Handling
if
(
!
(
data_out_valid
&&
!
data_out_ready
))
begin
// If data out handshake has been seen, drop valid
next_data_out_valid
=
1'b0
;
end
if
(
!
data_out_valid
)
begin
// No Data waiting at output
next_data_out
=
{
next_H
[
7
],
next_H
[
6
],
next_H
[
5
],
next_H
[
4
],
next_H
[
3
],
next_H
[
2
],
next_H
[
1
],
next_H
[
0
]
}
;
next_data_out_last
=
1'b1
;
next_data_out_valid
=
1'b1
;
// Next State Logic
next_state
=
3'd1
;
next_data_in_ready
=
1'b1
;
// Initialise Hash Value Registers
next_H
[
0
]
=
32'h6a09e667
;
next_H
[
1
]
=
32'hbb67ae85
;
next_H
[
2
]
=
32'h3c6ef372
;
next_H
[
3
]
=
32'ha54ff53a
;
next_H
[
4
]
=
32'h510e527f
;
next_H
[
5
]
=
32'h9b05688c
;
next_H
[
6
]
=
32'h1f83d9ab
;
next_H
[
7
]
=
32'h5be0cd19
;
end
else
begin
// Still Waiting for previous data to be recieved
next_state
=
3'd4
;
next_data_in_ready
=
1'b0
;
end
end
endcase
end
endmodule
\ No newline at end of file
This diff is collapsed.
Click to expand it.
hdl/src/sha_2_pkg.sv
+
95
−
93
View file @
b34860b7
...
...
@@ -16,122 +16,124 @@ package sha_2_pkg;
function
logic
[
data_width
-
1
:
0
]
ssig0
(
logic
[
data_width
-
1
:
0
]
x
);
logic
[
data_width
-
1
:
0
]
xrotr7
,
xrotr18
,
xshr3
;
assign
xrotr7
=
{
x
[
6
:
0
],
x
[
31
:
7
]
}
;
assign
xrotr18
=
{
x
[
17
:
0
],
x
[
31
:
18
]
}
;
assign
xshr3
=
x
>>
3
;
assign
ssig0
=
xrotr7
^
xrotr18
^
xshr3
;
xrotr7
=
(
x
<<
25
)
|
(
x
>>
7
)
;
xrotr18
=
(
x
<<
14
)
|
(
x
>>
18
)
;
xshr3
=
x
>>
3
;
ssig0
=
xrotr7
^
xrotr18
^
xshr3
;
endfunction
function
logic
[
data_width
-
1
:
0
]
ssig1
(
logic
[
data_width
-
1
:
0
]
x
);
logic
[
data_width
-
1
:
0
]
xrotr17
,
xrotr19
,
xshr10
;
assign
xrotr17
=
{
x
[
16
:
0
],
x
[
31
:
17
]
}
;
assign
xrotr1
9
=
{
x
[
18
:
0
],
x
[
31
:
19
]
}
;
assign
xshr10
=
x
>>
10
;
assign
ssig1
=
xrotr17
^
xrotr19
^
xshr10
;
xrotr17
=
(
x
<<
15
)
|
(
x
>>
17
)
;
xrotr1
7
=
(
x
<<
13
)
|
(
x
>>
19
)
;
xshr10
=
x
>>
10
;
ssig1
=
xrotr17
^
xrotr19
^
xshr10
;
endfunction
function
logic
[
data_width
-
1
:
0
]
bsig0
(
logic
[
data_width
-
1
:
0
]
x
);
logic
[
data_width
-
1
:
0
]
xrotr2
,
xrotr13
,
xrotr22
;
assign
xrotr2
=
{
x
[
1
:
0
],
x
[
31
:
2
]
}
;
assign
xrotr13
=
{
x
[
12
:
0
],
x
[
31
:
13
]
}
;
assign
xrotr22
=
{
x
[
21
:
0
],
x
[
31
:
22
]
}
;
assign
bsig0
=
xrotr2
^
xrotr13
^
xrotr22
;
xrotr2
=
(
x
<<
30
)
|
(
x
>>
2
)
;
xrotr13
=
(
x
<<
19
)
|
(
x
>>
13
)
;
xrotr22
=
(
x
<<
10
)
|
(
x
>>
22
)
;
bsig0
=
xrotr2
^
xrotr13
^
xrotr22
;
endfunction
function
logic
[
data_width
-
1
:
0
]
bsig1
(
logic
[
data_width
-
1
:
0
]
x
);
logic
[
data_width
-
1
:
0
]
xrotr6
,
xrotr11
,
xrotr25
;
assign
xrotr6
=
{
x
[
5
:
0
],
x
[
31
:
6
]
}
;
assign
xrotr11
=
{
x
[
10
:
0
],
x
[
31
:
11
]
}
;
assign
xrotr25
=
{
x
[
24
:
0
],
x
[
31
:
25
]
}
;
assign
bsig1
=
xrotr6
^
xrotr11
^
xrotr25
;
xrotr6
=
(
x
<<
26
)
|
(
x
>>
6
)
;
xrotr11
=
(
x
<<
21
)
|
(
x
>>
11
)
;
xrotr25
=
(
x
<<
7
)
|
(
x
>>
25
)
;
bsig1
=
xrotr6
^
xrotr11
^
xrotr25
;
endfunction
function
logic
[
data_width
-
1
:
0
]
ch
(
logic
[
data_width
-
1
:
0
]
x
,
y
,
z
);
assign
ch
=
(
x
&
y
)
^
((
~
x
)
&
z
);
ch
=
(
x
&
y
)
^
((
~
x
)
&
z
);
endfunction
function
logic
[
data_width
-
1
:
0
]
maj
(
logic
[
data_width
-
1
:
0
]
x
,
y
,
z
);
assign
maj
=
(
x
&
y
)
^
(
x
&
z
)
^
(
y
&
z
);
maj
=
(
x
&
y
)
^
(
x
&
z
)
^
(
y
&
z
);
endfunction
// SHA-2 Constants
const
logic
[
31
:
0
]
K0
=
32'h428a2f98
;
const
logic
[
31
:
0
]
K1
=
32'h71374491
;
const
logic
[
31
:
0
]
K2
=
32'hb5c0fbcf
;
const
logic
[
31
:
0
]
K3
=
32'he9b5dba5
;
const
logic
[
31
:
0
]
K4
=
32'h3956c25b
;
const
logic
[
31
:
0
]
K5
=
32'h59f111f1
;
const
logic
[
31
:
0
]
K6
=
32'h923f82a4
;
const
logic
[
31
:
0
]
K7
=
32'hab1c5ed5
;
const
logic
[
31
:
0
]
K8
=
32'hd807aa98
;
const
logic
[
31
:
0
]
K9
=
32'h12835b01
;
const
logic
[
31
:
0
]
K10
=
32'h243185be
;
const
logic
[
31
:
0
]
K11
=
32'h550c7dc3
;
const
logic
[
31
:
0
]
K12
=
32'h72be5d74
;
const
logic
[
31
:
0
]
K13
=
32'h80deb1fe
;
const
logic
[
31
:
0
]
K14
=
32'h9bdc06a7
;
const
logic
[
31
:
0
]
K15
=
32'hc19bf174
;
const
logic
[
31
:
0
]
K16
=
32'he49b69c1
;
const
logic
[
31
:
0
]
K17
=
32'hefbe4786
;
const
logic
[
31
:
0
]
K18
=
32'h0fc19dc6
;
const
logic
[
31
:
0
]
K19
=
32'h240ca1cc
;
const
logic
[
31
:
0
]
K20
=
32'h2de92c6f
;
const
logic
[
31
:
0
]
K21
=
32'h4a7484aa
;
const
logic
[
31
:
0
]
K22
=
32'h5cb0a9dc
;
const
logic
[
31
:
0
]
K23
=
32'h76f988da
;
const
logic
[
31
:
0
]
K24
=
32'h983e5152
;
const
logic
[
31
:
0
]
K25
=
32'ha831c66d
;
const
logic
[
31
:
0
]
K26
=
32'hb00327c8
;
const
logic
[
31
:
0
]
K27
=
32'hbf597fc7
;
const
logic
[
31
:
0
]
K28
=
32'hc6e00bf3
;
const
logic
[
31
:
0
]
K29
=
32'hd5a79147
;
const
logic
[
31
:
0
]
K30
=
32'h06ca6351
;
const
logic
[
31
:
0
]
K31
=
32'h14292967
;
const
logic
[
31
:
0
]
K32
=
32'h27b70a85
;
const
logic
[
31
:
0
]
K33
=
32'h2e1b2138
;
const
logic
[
31
:
0
]
K34
=
32'h4d2c6dfc
;
const
logic
[
31
:
0
]
K35
=
32'h53380d13
;
const
logic
[
31
:
0
]
K36
=
32'h650a7354
;
const
logic
[
31
:
0
]
K37
=
32'h766a0abb
;
const
logic
[
31
:
0
]
K38
=
32'h81c2c92e
;
const
logic
[
31
:
0
]
K39
=
32'h92722c85
;
const
logic
[
31
:
0
]
K40
=
32'ha2bfe8a1
;
const
logic
[
31
:
0
]
K41
=
32'ha81a664b
;
const
logic
[
31
:
0
]
K42
=
32'hc24b8b70
;
const
logic
[
31
:
0
]
K43
=
32'hc76c51a3
;
const
logic
[
31
:
0
]
K44
=
32'hd192e819
;
const
logic
[
31
:
0
]
K45
=
32'hd6990624
;
const
logic
[
31
:
0
]
K46
=
32'hf40e3585
;
const
logic
[
31
:
0
]
K47
=
32'h106aa070
;
const
logic
[
31
:
0
]
K48
=
32'h19a4c116
;
const
logic
[
31
:
0
]
K49
=
32'h1e376c08
;
const
logic
[
31
:
0
]
K50
=
32'h2748774c
;
const
logic
[
31
:
0
]
K51
=
32'h34b0bcb5
;
const
logic
[
31
:
0
]
K52
=
32'h391c0cb3
;
const
logic
[
31
:
0
]
K53
=
32'h4ed8aa4a
;
const
logic
[
31
:
0
]
K54
=
32'h5b9cca4f
;
const
logic
[
31
:
0
]
K55
=
32'h682e6ff3
;
const
logic
[
31
:
0
]
K56
=
32'h748f82ee
;
const
logic
[
31
:
0
]
K57
=
32'h78a5636f
;
const
logic
[
31
:
0
]
K58
=
32'h84c87814
;
const
logic
[
31
:
0
]
K59
=
32'h8cc70208
;
const
logic
[
31
:
0
]
K60
=
32'h90befffa
;
const
logic
[
31
:
0
]
K61
=
32'ha4506ceb
;
const
logic
[
31
:
0
]
K62
=
32'hbef9a3f7
;
const
logic
[
31
:
0
]
K63
=
32'hc67178f2
;
// H_init Constants
const
logic
[
31
:
0
]
H0_init
=
32'h6a09e667
;
const
logic
[
31
:
0
]
H1_init
=
32'hbb67ae85
;
const
logic
[
31
:
0
]
H2_init
=
32'h3c6ef372
;
const
logic
[
31
:
0
]
H3_init
=
32'ha54ff53a
;
const
logic
[
31
:
0
]
H4_init
=
32'h510e527f
;
const
logic
[
31
:
0
]
H5_init
=
32'h9b05688c
;
const
logic
[
31
:
0
]
H6_init
=
32'h1f83d9ab
;
const
logic
[
31
:
0
]
H7_init
=
32'h5be0cd19
;
// // // SHA-2 Constants
// logic [31:0] K [63:0];
// assign K[0] = 32'h428a2f98;
// assign K[1] = 32'h71374491;
// assign K[2] = 32'hb5c0fbcf;
// assign K[3] = 32'he9b5dba5;
// assign K[4] = 32'h3956c25b;
// assign K[5] = 32'h59f111f1;
// assign K[6] = 32'h923f82a4;
// assign K[7] = 32'hab1c5ed5;
// assign K[8] = 32'hd807aa98;
// assign K[9] = 32'h12835b01;
// assign K[10] = 32'h243185be;
// assign K[11] = 32'h550c7dc3;
// assign K[12] = 32'h72be5d74;
// assign K[13] = 32'h80deb1fe;
// assign K[14] = 32'h9bdc06a7;
// assign K[15] = 32'hc19bf174;
// assign K[16] = 32'he49b69c1;
// assign K[17] = 32'hefbe4786;
// assign K[18] = 32'h0fc19dc6;
// assign K[19] = 32'h240ca1cc;
// assign K[20] = 32'h2de92c6f;
// assign K[21] = 32'h4a7484aa;
// assign K[22] = 32'h5cb0a9dc;
// assign K[23] = 32'h76f988da;
// assign K[24] = 32'h983e5152;
// assign K[25] = 32'ha831c66d;
// assign K[26] = 32'hb00327c8;
// assign K[27] = 32'hbf597fc7;
// assign K[28] = 32'hc6e00bf3;
// assign K[29] = 32'hd5a79147;
// assign K[30] = 32'h06ca6351;
// assign K[31] = 32'h14292967;
// assign K[32] = 32'h27b70a85;
// assign K[33] = 32'h2e1b2138;
// assign K[34] = 32'h4d2c6dfc;
// assign K[35] = 32'h53380d13;
// assign K[36] = 32'h650a7354;
// assign K[37] = 32'h766a0abb;
// assign K[38] = 32'h81c2c92e;
// assign K[39] = 32'h92722c85;
// assign K[40] = 32'ha2bfe8a1;
// assign K[41] = 32'ha81a664b;
// assign K[42] = 32'hc24b8b70;
// assign K[43] = 32'hc76c51a3;
// assign K[44] = 32'hd192e819;
// assign K[45] = 32'hd6990624;
// assign K[46] = 32'hf40e3585;
// assign K[47] = 32'h106aa070;
// assign K[48] = 32'h19a4c116;
// assign K[49] = 32'h1e376c08;
// assign K[50] = 32'h2748774c;
// assign K[51] = 32'h34b0bcb5;
// assign K[52] = 32'h391c0cb3;
// assign K[53] = 32'h4ed8aa4a;
// assign K[54] = 32'h5b9cca4f;
// assign K[55] = 32'h682e6ff3;
// assign K[56] = 32'h748f82ee;
// assign K[57] = 32'h78a5636f;
// assign K[58] = 32'h84c87814;
// assign K[59] = 32'h8cc70208;
// assign K[60] = 32'h90befffa;
// assign K[61] = 32'ha4506ceb;
// assign K[62] = 32'hbef9a3f7;
// assign K[63] = 32'hc67178f2;
// // H_init Constants
// const logic [31:0] H0_init = 32'h6a09e667;
// const logic [31:0] H1_init = 32'hbb67ae85;
// const logic [31:0] H2_init = 32'h3c6ef372;
// const logic [31:0] H3_init = 32'ha54ff53a;
// const logic [31:0] H4_init = 32'h510e527f;
// const logic [31:0] H5_init = 32'h9b05688c;
// const logic [31:0] H6_init = 32'h1f83d9ab;
// const logic [31:0] H7_init = 32'h5be0cd19;
endpackage
\ No newline at end of file
This diff is collapsed.
Click to expand it.
hdl/verif/tb_hash_process.sv
+
21
−
9
View file @
b34860b7
...
...
@@ -9,9 +9,9 @@
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`timescale
1
ns
/
1
ns
`include
"
message_build
.sv"
`include
"
hash_process
.sv"
module
tb_
message_build
;
module
tb_
hash_process
;
logic
clk
;
logic
nrst
;
...
...
@@ -47,7 +47,6 @@ module tb_message_build;
.
data_out_ready
(
data_out_ready
));
logic
data_in_drive_en
;
logic
cfg_drive_en
;
logic
data_out_drive_ready
;
logic
[
511
:
0
]
data_in_queue
[$];
...
...
@@ -149,14 +148,24 @@ module tb_message_build;
logic
output_data_last
;
// Temporary Output Data Last
initial
begin
$
dumpfile
(
"engine_sim.vcd"
);
$
dumpvars
(
0
,
tb_message_build
);
$
dumpfile
(
"hash_process.vcd"
);
$
dumpvars
(
0
,
tb_hash_process
);
for
(
int
i
=
0
;
i
<
16
;
i
++
)
begin
$
dumpvars
(
0
,
tb_hash_process
.
uut
.
M
[
i
]);
end
for
(
int
i
=
0
;
i
<
8
;
i
++
)
begin
$
dumpvars
(
0
,
tb_hash_process
.
uut
.
H
[
i
]);
$
dumpvars
(
0
,
tb_hash_process
.
uut
.
next_H
[
i
]);
end
for
(
int
i
=
0
;
i
<
64
;
i
++
)
begin
$
dumpvars
(
0
,
tb_hash_process
.
uut
.
W
[
i
]);
$
dumpvars
(
0
,
tb_hash_process
.
uut
.
next_W
[
i
]);
end
data_in_drive_en
=
0
;
cfg_drive_en
=
0
;
data_out_drive_ready
=
0
;
// Read input data into Queue
fd
=
$
fopen
(
"../stimulus/input_data_builder_stim.csv"
,
"r"
);
fd
=
$
fopen
(
"../stimulus/
testbench/
input_data_builder_stim.csv"
,
"r"
);
while
($
fscanf
(
fd
,
"%x,%b"
,
input_data
,
input_data_last
)
==
2
)
begin
data_in_queue
.
push_back
(
input_data
);
data_in_last_queue
.
push_back
(
input_data_last
);
...
...
@@ -164,7 +173,7 @@ module tb_message_build;
$
fclose
(
fd
);
// Read output data into Queue
fd
=
$
fopen
(
"../stimulus/output_data_builder_stim.csv"
,
"r"
);
fd
=
$
fopen
(
"../stimulus/
testbench/
output_data_builder_stim.csv"
,
"r"
);
while
($
fscanf
(
fd
,
"%x,%b"
,
output_data
,
output_data_last
)
==
2
)
begin
data_out_queue
.
push_back
(
output_data
);
data_out_last_queue
.
push_back
(
output_data_last
);
...
...
@@ -181,9 +190,12 @@ module tb_message_build;
#
20
data_in_drive_en
=
1
;
// Write some data into the config register
#
30
cfg_drive_en
=
1
;
#
30
data_out_drive_ready
=
1
;
#
200000
$
display
(
"Test Complete"
);
$
finish
;
end
initial
begin
...
...
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