Updated flow and testbench and fixed bug in message builder

flow/socsim

@@ -15,4 +15,4 @@ DEFAULT_SIMULATOR="ivlog"
 if [[ -z "${SIMULATOR}" ]]; then 
     SIMULATOR=$DEFAULT_SIMULATOR
 fi
-$SHA_2_ACC_DIR"/simulate/simulators/"$SIMULATOR"_sim.sh"
+$SHA_2_ACC_DIR"/flow/simulators/"$SIMULATOR"_sim.sh"

hdl/src/message_build.sv

@@ -48,6 +48,12 @@ module message_build (
     // Combine Last Data (after being masked) with end marker and size
     assign last_data_word = (data_in & last_word_mask) | end_marker;
     
+    logic [53:0] word_extract;
+    logic [8:0]  rem_extract;
+    
+    assign word_extract = cfg_size[63:10];
+    assign rem_extract  = cfg_size[8:0];
+    
     always_ff @(posedge clk, negedge nrst) begin
         if ((!nrst) | sync_rst) begin
             state           <= 3'd0;
@@ -85,6 +91,7 @@ module message_build (
         case (state)
             3'd0: begin // First time State
                     next_cfg_ready = 1'b1;
+                    next_state     = 3'd1;
                 end
 
             3'd1: begin // Initial Config Read
@@ -93,8 +100,8 @@ module message_build (
                         next_cfg_size        = cfg_size;
                         next_cfg_ready       = 1'b0;
                         next_data_in_ready   = 1'b1;
-                        next_data_word_count = cfg_size[63:10] + {53'd0, |cfg_size[8:0]}; // Divide by 512 and round up
-                        next_data_word_rem   = cfg_size[8:0];
+                        next_data_word_count = word_extract + {53'd0, |rem_extract}; // Divide by 512 and round up
+                        next_data_word_rem   = rem_extract;
                         if (next_data_word_count > 1) begin
                             next_state = 3'd2;
                         end else begin

hdl/verif/tb_engine.sv

@@ -10,7 +10,7 @@
 //-----------------------------------------------------------------------------
 
 `timescale 1ns/1ns
-`include "sha_2_engine.sv"
+`include "message_build.sv"
 module tb_engine;
     
     logic clk;
@@ -31,7 +31,7 @@ module tb_engine;
     logic data_out_valid;
     logic data_out_ready;
         
-    sha_2_engine uut (
+    message_build uut (
                   .clk (clk),
                   .nrst(nrst),
                   .data_in(data_in),
@@ -72,18 +72,17 @@ module tb_engine;
         end
     end
     
-
     logic [511:0] temp_data ;
     
     initial begin
         $dumpfile("engine_sim.vcd");
         $dumpvars(0, tb_engine);
     
-        for (int idx = 0; idx < 4; idx = idx + 1) begin
-            $dumpvars(0, uut.data_in_fifo[idx]);
-            $dumpvars(0, uut.cfg_size_fifo[idx]);
-            $dumpvars(0, uut.cfg_scheme_fifo[idx]);
-        end
+        // for (int idx = 0; idx < 4; idx = idx + 1) begin
+        //     $dumpvars(0, uut.data_in_fifo   [idx]);
+        //     $dumpvars(0, uut.cfg_size_fifo  [idx]);
+        //     $dumpvars(0, uut.cfg_scheme_fifo[idx]);
+        // end
        
         data_in_drive_en = 0;
         
@@ -99,7 +98,7 @@ module tb_engine;
         cfg_scheme = 0;
         cfg_valid = 0;
         
-        data_out_ready = 0;
+        data_out_ready = 1;
         
         #20 nrst  = 1;
         #20 nrst  = 0;
@@ -108,7 +107,7 @@ module tb_engine;
        
         // Write some data into the config register
         # 30 
-        cfg_size = 512;
+        cfg_size = 448;
         cfg_scheme = 2;
         cfg_valid = 1;