changed format of generated values and read input data into testbench
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- hdl/verif/tb_engine.sv 16 additions, 16 deletionshdl/verif/tb_engine.sv
- model/py/builder.py 3 additions, 9 deletionsmodel/py/builder.py
- model/py/input_cfg_builder_stim.csv 9 additions, 10 deletionsmodel/py/input_cfg_builder_stim.csv
- model/py/input_data_builder_stim.csv 9 additions, 10 deletionsmodel/py/input_data_builder_stim.csv
- model/py/output_data_builder_stim.csv 9 additions, 10 deletionsmodel/py/output_data_builder_stim.csv
- simulate/sim/input_cfg_builder_stim.csv 9 additions, 0 deletionssimulate/sim/input_cfg_builder_stim.csv
- simulate/sim/input_data_builder_stim.csv 9 additions, 0 deletionssimulate/sim/input_data_builder_stim.csv
- simulate/sim/output_data_builder_stim.csv 9 additions, 0 deletionssimulate/sim/output_data_builder_stim.csv
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