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Commit 34f2e2ac authored by dam1n19's avatar dam1n19
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ATO2-24: Renamed RTL Modules with sha256 prefix

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...@@ -8,6 +8,9 @@ ...@@ -8,6 +8,9 @@
// //
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`include "sha256_hash_compression.sv"
`include "sha256_message_build.sv"
`include "fifo_vr.sv"
module sha256_engine ( module sha256_engine (
// Clocking Signals // Clocking Signals
...@@ -96,7 +99,7 @@ module sha256_engine ( ...@@ -96,7 +99,7 @@ module sha256_engine (
); );
// Message Build (Construct Message Blocks) // Message Build (Construct Message Blocks)
message_build message_block_builder ( sha256_message_build message_block_builder (
.clk (clk), .clk (clk),
.nrst (nrst), .nrst (nrst),
.en (en), .en (en),
...@@ -117,7 +120,7 @@ module sha256_engine ( ...@@ -117,7 +120,7 @@ module sha256_engine (
); );
// Hash Compression (Peform Hash Calculation) // Hash Compression (Peform Hash Calculation)
hash_compression hash_calculator ( sha256_hash_compression hash_calculator (
.clk (clk), .clk (clk),
.nrst (nrst), .nrst (nrst),
.en (en), .en (en),
......
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// SoC Labs Basic SHA-2 Hash Processing Module // SoC Labs Basic SHA-256 Hash Processing Module
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -8,10 +8,10 @@ ...@@ -8,10 +8,10 @@
// //
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`include "hashing_functions.sv" `include "sha256_hashing_functions.sv"
module hash_compression ( module sha256_hash_compression (
input logic clk, input logic clk,
input logic nrst, input logic nrst,
input logic en, input logic en,
...@@ -32,7 +32,7 @@ module hash_compression ( ...@@ -32,7 +32,7 @@ module hash_compression (
input logic data_out_ready input logic data_out_ready
); );
import hashing_functions::*; import sha256_hashing_functions::*;
// Message Chunks // Message Chunks
logic [31:0] M [15:0]; logic [31:0] M [15:0];
......
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// SoC Labs Basic SHA-2 Engine function and constants SV Package // SoC Labs Basic SHA-256 Engine function and constants SV Package
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
package hashing_functions; package sha256_hashing_functions;
parameter data_width = 32; parameter data_width = 32;
// SHA-2 Functions // SHA-2 Functions
......
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// SoC Labs Basic SHA-2 Message Builder Module // SoC Labs Basic SHA-256 Message Builder Module
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. // A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
// //
// Contributors // Contributors
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
// //
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module message_build ( module sha256_message_build (
input logic clk, input logic clk,
input logic nrst, input logic nrst,
input logic en, input logic en,
......
...@@ -9,9 +9,9 @@ ...@@ -9,9 +9,9 @@
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`timescale 1ns/1ns `timescale 1ns/1ns
`include "message_build.sv" `include "sha256_engine.sv"
module tb_message_build; module tb_sha256_engine;
logic clk; logic clk;
logic nrst; logic nrst;
......
...@@ -9,9 +9,9 @@ ...@@ -9,9 +9,9 @@
// Copyright 2022, SoC Labs (www.soclabs.org) // Copyright 2022, SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
`timescale 1ns/1ns `timescale 1ns/1ns
`include "hash_compression.sv" `include "sha256_hash_compression.sv"
module tb_hash_compression; module tb_sha256_hash_compression;
logic clk; logic clk;
logic nrst; logic nrst;
...@@ -36,7 +36,7 @@ module tb_hash_compression; ...@@ -36,7 +36,7 @@ module tb_hash_compression;
logic data_out_ready; logic data_out_ready;
logic data_out_last; logic data_out_last;
hash_compression uut ( sha256_hash_compression uut (
.clk (clk), .clk (clk),
.nrst(nrst), .nrst(nrst),
.en (en), .en (en),
...@@ -154,19 +154,19 @@ module tb_hash_compression; ...@@ -154,19 +154,19 @@ module tb_hash_compression;
logic output_data_last; // Temporary Output Data Last logic output_data_last; // Temporary Output Data Last
initial begin initial begin
$dumpfile("hash_compression.vcd"); $dumpfile("sha256_hash_compression.vcd");
$dumpvars(0, tb_hash_compression); $dumpvars(0, tb_sha256_hash_compression);
for (int i = 0; i < 16; i++) begin for (int i = 0; i < 16; i++) begin
$dumpvars(0, tb_hash_compression.uut.M[i]); $dumpvars(0, tb_sha256_hash_compression.uut.M[i]);
end end
for (int i = 0; i < 8; i++) begin for (int i = 0; i < 8; i++) begin
$dumpvars(0, tb_hash_compression.uut.H[i]); $dumpvars(0, tb_sha256_hash_compression.uut.H[i]);
$dumpvars(0, tb_hash_compression.uut.next_H[i]); $dumpvars(0, tb_sha256_hash_compression.uut.next_H[i]);
end end
for (int i = 0; i < 64; i++) begin for (int i = 0; i < 64; i++) begin
$dumpvars(0, tb_hash_compression.uut.W[i]); $dumpvars(0, tb_sha256_hash_compression.uut.W[i]);
$dumpvars(0, tb_hash_compression.uut.next_W[i]); $dumpvars(0, tb_sha256_hash_compression.uut.next_W[i]);
$dumpvars(0, tb_hash_compression.uut.ssig1_next_W[i]); $dumpvars(0, tb_sha256_hash_compression.uut.ssig1_next_W[i]);
end end
data_in_drive_en = 0; data_in_drive_en = 0;
data_out_drive_ready = 0; data_out_drive_ready = 0;
......
//-----------------------------------------------------------------------------
// SoC Labs Basic SHA-2 Message Builder Testbench
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright 2022, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`timescale 1ns/1ns
`include "sha256_message_build.sv"
module tb_sha256_message_build;
logic clk;
logic nrst;
logic en;
logic sync_rst;
// Data In data and Handshaking
logic [511:0] data_in;
logic data_in_last;
logic data_in_valid;
logic data_in_ready;
// Config data and Handshaking
logic [63:0] cfg_size;
logic [1:0] cfg_scheme;
logic cfg_last;
logic cfg_valid;
logic cfg_ready;
// Data Out data and Handshaking
logic [511:0] data_out;
logic data_out_valid;
logic data_out_ready;
logic data_out_last;
sha256_message_build uut (
.clk (clk),
.nrst(nrst),
.en (en),
.sync_rst(sync_rst),
.data_in(data_in),
.data_in_valid(data_in_valid),
.data_in_ready(data_in_ready),
.data_in_last(data_in_last),
.cfg_size(cfg_size),
.cfg_scheme(cfg_scheme),
.cfg_last(cfg_last),
.cfg_valid(cfg_valid),
.cfg_ready(cfg_ready),
.data_out(data_out),
.data_out_last(data_out_last),
.data_out_valid(data_out_valid),
.data_out_ready(data_out_ready));
logic data_in_drive_en;
logic cfg_drive_en;
logic data_out_drive_ready;
logic [511:0] data_in_queue [$];
logic data_in_last_queue [$];
logic data_in_wait_queue;
logic [63:0] cfg_size_queue [$];
logic [1:0] cfg_scheme_queue [$];
logic cfg_last_queue [$];
logic cfg_wait_queue;
logic [511:0] data_out_queue [$];
logic data_out_last_queue [$];
logic data_out_wait_queue;
// Handle Valid and Data for data_in
always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
if (!nrst) begin
data_in <= 512'd0;
data_in_valid <= 1'b0;
data_in_last <= 1'b0;
data_in_wait_queue <= 1'b1;
end else if (data_in_drive_en) begin
if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
(data_in_wait_queue == 1'b1)) begin
// Data transfer just completed or transfers already up to date
if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0)) begin
data_in <= data_in_queue.pop_front();
data_in_last <= data_in_last_queue.pop_front();
data_in_valid <= 1'b1;
data_in_wait_queue <= 1'b0;
end else begin
// No data currently avaiable in queue to write but transfers up to date
data_in_wait_queue <= 1'b1;
data_in_valid <= 1'b0;
end
end
end
end
// Handle Valid and Data for cfg
always_ff @(posedge clk, negedge nrst) begin: cfg_valid_drive
if (!nrst) begin
cfg_size <= 64'd0;
cfg_scheme <= 2'd0;
cfg_valid <= 1'b0;
cfg_last <= 1'b0;
cfg_wait_queue <= 1'b1;
end else if (cfg_drive_en) begin
if (((cfg_valid == 1'b1) && (cfg_ready == 1'b1)) ||
(cfg_wait_queue == 1'b1)) begin
// cfg transfer just completed or transfers already up to date
if ((cfg_size_queue.size() > 0) && (cfg_scheme_queue.size() > 0 ) && (cfg_last_queue.size() > 0)) begin
cfg_size <= cfg_size_queue.pop_front();
cfg_scheme <= cfg_scheme_queue.pop_front();
cfg_last <= cfg_last_queue.pop_front();
cfg_valid <= 1'b1;
cfg_wait_queue <= 1'b0;
end else begin
// No data currently avaiable in queue to write but transfers up to date
cfg_wait_queue <= 1'b1;
cfg_valid <= 1'b0;
end
end
end
end
logic [511:0] data_out_check;
logic data_out_last_check;
logic check_output;
logic test_end;
int packet_num;
// Handle Output Ready Driving
always_ff @(posedge clk, negedge nrst) begin: data_out_recieve
if (!nrst) begin
data_out_ready <= 1'b0;
check_output <= 1'b0;
test_end <= 1'b0;
end else begin
// Synchronise Ready to Clock
if (data_out_drive_ready) begin
data_out_ready <= 1'b1;
end else begin
data_out_ready <= 1'b0;
end
end
end
// Handle Output Data Verification
always @(posedge clk) begin
// Check Data on Handshake
if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
assert (data_out == data_out_check) else begin
$error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
$finish;
end
// $display("data_out match! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
assert (data_out_last == data_out_last_check) else begin
$error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
$finish;
end
// $display("data_out_last match! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
data_out_check <= data_out_queue.pop_front();
data_out_last_check <= data_out_last_queue.pop_front();
if (data_out_last_check == 1'b1) begin
packet_num <= packet_num + 1;
end
end else begin
$display("Test Passes");
$finish;
end
end
end
// File Reading Variables
int fd; // File descriptor Handle
logic [511:0] input_data; // Temporary Input Data Storage
logic input_data_last; // Temporary Input Data Last
logic [63:0] input_cfg_size; // Temporary cfg size
logic [1:0] input_cfg_scheme; // Temporary cfg scheme
logic input_cfg_last; // Temporary cfg last;
logic [511:0] output_data; // Temporary Output Data Storage
logic output_data_last; // Temporary Output Data Last
initial begin
$dumpfile("sha256_message_build.vcd");
$dumpvars(0, tb_sha256_message_build);
data_in_drive_en = 0;
cfg_drive_en = 0;
data_out_drive_ready = 0;
// Read input data into Queue
fd = $fopen("../stimulus/testbench/input_data_stim.csv", "r");
while ($fscanf (fd, "%x,%b", input_data, input_data_last) == 2) begin
data_in_queue.push_back(input_data);
data_in_last_queue.push_back(input_data_last);
end
$fclose(fd);
// Read input cfg into Queue
fd = $fopen("../stimulus/testbench/input_cfg_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%b", input_cfg_size, input_cfg_scheme, input_cfg_last) == 3) begin
cfg_size_queue.push_back(input_cfg_size);
cfg_scheme_queue.push_back(input_cfg_scheme);
cfg_last_queue.push_back(input_cfg_last);
end
$fclose(fd);
// Read output data into Queue
fd = $fopen("../stimulus/testbench/inout_message_block_stim_ref.csv", "r");
while ($fscanf (fd, "%x,%b", output_data, output_data_last) == 2) begin
data_out_queue.push_back(output_data);
data_out_last_queue.push_back(output_data_last);
end
$fclose(fd);
// Initialise First Checking Values
data_out_check = data_out_queue.pop_front();
data_out_last_check = data_out_last_queue.pop_front();
// Defaultly enable Message Builder
en = 1;
// Defaultly set Sync Reset Low
sync_rst = 0;
#20 nrst = 1;
#20 nrst = 0;
#20 nrst = 1;
#20 data_in_drive_en = 1;
// Write some data into the config register
# 30 cfg_drive_en = 1;
# 30 data_out_drive_ready = 1;
end
initial begin
forever begin
#10 clk = 0;
#10 clk = 1;
end
end
endmodule
\ No newline at end of file
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