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SoCLabs
SoCLabs SHA-2 Accelerator
Commits
1da6f1d5
Commit
1da6f1d5
authored
2 years ago
by
dam1n19
Browse files
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ATO2-55
: Added Fullness Status Signal to FIFO and passed it out as status signal
parent
11e75463
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3 changed files
hdl/src/fifo_vr.sv
+6
-1
6 additions, 1 deletion
hdl/src/fifo_vr.sv
hdl/src/sha256_id_buf.sv
+15
-7
15 additions, 7 deletions
hdl/src/sha256_id_buf.sv
hdl/verif/tb_sha256_id_buf.sv
+1
-1
1 addition, 1 deletion
hdl/verif/tb_sha256_id_buf.sv
with
22 additions
and
9 deletions
hdl/src/fifo_vr.sv
+
6
−
1
View file @
1da6f1d5
...
...
@@ -30,7 +30,10 @@ module fifo_vr #(
output
logic
[
DATA_W
-
1
:
0
]
data_out
,
output
logic
data_out_last
,
input
logic
data_out_ready
,
output
logic
data_out_valid
output
logic
data_out_valid
,
// Status
output
logic
[
PTR_W
-
1
:
0
]
status_ptr_dif
);
logic
data_in_shake
;
// Successful Write Handshake
...
...
@@ -46,6 +49,8 @@ module fifo_vr #(
assign
ptr_dif
=
write_ptr
-
read_ptr
;
assign
status_ptr_dif
=
ptr_dif
;
// EXAMPLE: Conditions to write and read from FIFO's
// Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read
// 000 - 000 = 000 | Y | N
...
...
This diff is collapsed.
Click to expand it.
hdl/src/sha256_id_buf.sv
+
15
−
7
View file @
1da6f1d5
...
...
@@ -10,7 +10,11 @@
//-----------------------------------------------------------------------------
`include
"fifo_vr.sv"
module
sha256_id_buf
(
module
sha256_id_buf
#(
parameter
DEPTH
=
4
,
parameter
ID_DATA_W
=
6
,
parameter
PTR_W
=
$
clog2
(
DEPTH
)
// Read/Write Pointer Width
)(
input
logic
clk
,
input
logic
nrst
,
input
logic
en
,
...
...
@@ -19,23 +23,25 @@ module sha256_id_buf (
input
logic
sync_rst
,
// ID In
input
logic
[
5
:
0
]
id_in
,
input
logic
[
ID_DATA_W
-
1
:
0
]
id_in
,
input
logic
id_in_last
,
input
logic
id_in_valid
,
output
logic
id_in_ready
,
// ID Out
output
logic
[
5
:
0
]
id_out
,
output
logic
[
ID_DATA_W
-
1
:
0
]
id_out
,
output
logic
id_out_last
,
output
logic
id_out_valid
,
input
logic
id_out_ready
,
// Status Out
output
logic
[
5
:
0
]
status_id
output
logic
[
ID_DATA_W
-
1
:
0
]
status_id
,
// ID being passed to Validator
output
logic
[
PTR_W
:
0
]
status_buffered_ids
// Number of IDs in ID Validation Queue
);
fifo_vr
#(
8
,
// Depth
6
// Data Width
logic
[
PTR_W
:
0
]
status_ptr_dif
;
fifo_vr
#(
DEPTH
,
// Depth
ID_DATA_W
// Data Width
)
id_buffer
(
.
clk
(
clk
),
.
nrst
(
nrst
),
...
...
@@ -48,10 +54,12 @@ module sha256_id_buf (
.
data_out
(
id_out
),
.
data_out_last
(
id_out_last
),
.
data_out_valid
(
id_out_valid
),
.
data_out_ready
(
id_out_ready
)
.
data_out_ready
(
id_out_ready
),
.
status_ptr_dif
(
status_ptr_dif
)
);
// Status Signal Logic
// - status ID is updated when id_out is updated
assign
status_buffered_ids
=
status_ptr_dif
;
assign
status_id
=
id_out
;
endmodule
\ No newline at end of file
This diff is collapsed.
Click to expand it.
hdl/verif/tb_sha256_id_buf.sv
+
1
−
1
View file @
1da6f1d5
...
...
@@ -217,7 +217,7 @@ module tb_sha256_id_buf;
// Read output data into Queue
fd
=
$
fopen
(
"../stimulus/testbench/output_buf_id_ref.csv"
,
"r"
);
while
($
fscanf
(
fd
,
"%
x
,%b,%
b
,%d"
,
temp_id_out
,
temp_id_out_last
,
temp_status_id_out
,
temp_id_out_stall
)
==
4
)
begin
while
($
fscanf
(
fd
,
"%
d
,%b,%
d
,%d"
,
temp_id_out
,
temp_id_out_last
,
temp_status_id_out
,
temp_id_out_stall
)
==
4
)
begin
id_out_queue
.
push_back
(
temp_id_out
);
id_out_last_queue
.
push_back
(
temp_id_out_last
);
status_id_out_queue
.
push_back
(
temp_status_id_out
);
...
...
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