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Commit 9f9a9c73 authored by dam1n19's avatar dam1n19
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Updated set_env and changed nanosoc instantiation parameters

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flist/project/wrapper.flist
+ 5
− 2
View file @ 9f9a9c73
......@@ -12,7 +12,7 @@
// Abstract : Verilog Command File for Top-level Accelerator Wrapper
//-----------------------------------------------------------------------------
// DESIGN_TOP your_wrapper
// DESIGN_TOP wrapper_accelerator
// ============= Verilog library extensions ===========
+libext+.v+.vlib
......@@ -20,9 +20,12 @@
// ============= Wrapper IP Filelist ========================
-f $(PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
// - Corstone-101 System components
-f $(PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/wrapper/src/
+incdir+$(PROJECT_DIR)/wrapper/src/
// Add the source files related to your custom wrapper
// $(PROJECT_DIR)/wrapper/src/your_wrapper.v
$(PROJECT_DIR)/wrapper/src/wrapper_accelerator.sv
set_env.sh
+ 3
− 0
View file @ 9f9a9c73
......@@ -32,6 +32,9 @@ else
export DESIGN_ROOT
fi
# Add in location for socsim scripts
export SOCSIM_PATH=$PROJECT_DIR/simulate/socsim
# Source dependency environment variable script
source $PROJECT_DIR/env/dependency_env.sh
......
system/src/nanosoc_exp.v
+ 25
− 4
View file @ 9f9a9c73
......@@ -13,7 +13,7 @@
module nanosoc_exp #(
parameter ADDRWIDTH=29, // Region Address Width
parameter ACCEL_ADDRWIDTH=12 // Region Address Width
parameter ACCEL_ADDRWIDTH=13 // Region Address Width
)(
input wire HCLK, // Clock
input wire HRESETn, // Reset
......@@ -58,7 +58,7 @@ wire [31:0] HRDATA1;
// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default target
assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
assign HSEL0 = (HADDRS[ADDRWIDTH-1:16] < 'h200) ? 1'b1:1'b0;
assign HSEL1 = HSEL0 ? 1'b0:1'b1;
//********************************************************************************
......@@ -131,8 +131,29 @@ cmsdk_ahb_slave_mux #(
//********************************************************************************
// Slave module 1: Accelerator AHB target module
//********************************************************************************
wrapper_accelerator #(ACCEL_ADDRWIDTH
) u_accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
// Input target port: 32 bit data bus interface
.HSELS (HSEL0),
.HADDRS (HADDRS[ACCEL_ADDRWIDTH-1:0]),
.HTRANSS (HTRANSS),
.HSIZES (HSIZES),
.HPROTS (HPROTS),
.HWRITES (HWRITES),
.HREADYS (HREADYS),
.HWDATAS (HWDATAS),
.HREADYOUTS (HREADYOUT0),
.HRESPS (HRESP0),
.HRDATAS (HRDATA0),
.in_data_req (ip_data_req),
.out_data_req (op_data_req)
);
// Instantiate your accelerator wrapper HERE
//********************************************************************************
// Slave module 2: AHB default target module
......@@ -144,7 +165,7 @@ cmsdk_ahb_slave_mux #(
.HTRANS (HTRANSS),
.HREADY (HREADYS),
.HREADYOUT (HREADYOUT1),
.HRESP (HRESPS)
.HRESP (HRESP1)
);
assign HRDATA1 = {32{1'b0}}; // Default target don't have data
......
wrapper/src/wrapper_accelerator.sv
+ 51
− 50
View file @ 9f9a9c73
......@@ -10,7 +10,7 @@
//-----------------------------------------------------------------------------
module wrapper_accelerator #(
parameter AHBADDRWIDTH=12,
parameter AHBADDRWIDTH=13,
parameter INPACKETWIDTH=512,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
......@@ -57,7 +57,7 @@ module wrapper_accelerator #(
localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
// Control and Status Register Parameters
localparam [AHBADDRWIDTH-1:0] CSRADDR = 'h800;
localparam [AHBADDRWIDTH-1:0] CSRADDR = 'h1000;
localparam CSRADDRWIDTH = AHBADDRWIDTH - 2;
//**********************************************************
......@@ -94,7 +94,7 @@ module wrapper_accelerator #(
// Internal AHB Address Assignment
assign hsel0 = ((HADDRS < OUTPORTADDR) && (HADDRS >= INPORTADDR)) ? 1'b1:1'b0; // Input Port Select
assign hsel1 = ((HADDRS < CSRADDR) && (HADDRS >= OUTPORTADDR)) ? 1'b1:1'b0; // Output Port Select
assign hsel1 = ((HADDRS < CSRADDR) && (HADDRS >= OUTPORTADDR)) ? 1'b1:1'b0; // Output Port Select
assign hsel2 = (HADDRS >= CSRADDR) ? 1'b1:1'b0; // CSR Select
assign hsel3 = (hsel0 | hsel1 | hsel2) ? 1'b0:1'b1; // Default Target Select
......@@ -367,21 +367,22 @@ module wrapper_accelerator #(
logic ctrl_reg_write_en, ctrl_reg_read_en;
assign ctrl_reg_write_en = csr_reg_write_en & (csr_reg_addr < 10'h100);
assign ctrl_reg_read_en = csr_reg_read_en & (csr_reg_addr < 10'h100);
// // Example Register Block
// cmsdk_apb3_eg_slave_reg #(
// CSRADDRWIDTH
// ) u_csr_block (
// .pclk (HCLK),
// .presetn (HRESETn),
// // Register interface
// .addr (csr_reg_addr),
// .read_en (csr_reg_read_en),
// .write_en (csr_reg_write_en),
// .wdata (csr_reg_wdata),
// .ecorevnum (4'd0),
// .rdata (csr_reg_rdata)
// );
cmsdk_apb3_eg_slave_reg #(
CSRADDRWIDTH
) u_csr_block (
.pclk (HCLK),
.presetn (HRESETn),
// Register interface
.addr (csr_reg_addr),
.read_en (csr_reg_read_en),
.write_en (csr_reg_write_en),
.wdata (csr_reg_wdata),
.ecorevnum (4'd0),
.rdata (csr_reg_rdata)
);
//----------------------------------------------------------
// Default AHB Target Logic
......@@ -411,39 +412,39 @@ module wrapper_accelerator #(
// Wrapper DMA Data Request Generation
//**********************************************************
wrapper_req_ctrl_reg #(
CSRADDRWIDTH
) u_wrapper_req_ctrl_reg (
.hclk (HCLK),
.hresetn (HRESETn),
.addr (csr_reg_addr),
.read_en (ctrl_reg_read_en),
.write_en (ctrl_reg_write_en),
.wdata (csr_reg_wdata),
.rdata (csr_reg_rdata),
// Data Transfer Request Signaling
.req_act_ch0 (in_dma_req_act),
.req_act_ch1 (out_dma_req_act),
.req_act_ch2 (1'b0),
.req_act_ch3 (1'b0),
.req_act_ch4 (1'b0),
// DMA Request Output
.drq_ch0 (in_data_req),
.drq_ch1 (out_data_req),
.drq_ch2 (),
.drq_ch3 (),
.drq_ch4 (),
// Interrupt Request Output
.irq_ch0 (),
.irq_ch1 (),
.irq_ch2 (),
.irq_ch3 (),
.irq_ch4 (),
.irq_merged ()
);
// wrapper_req_ctrl_reg #(
// CSRADDRWIDTH
// ) u_wrapper_req_ctrl_reg (
// .hclk (HCLK),
// .hresetn (HRESETn),
// .addr (csr_reg_addr),
// .read_en (ctrl_reg_read_en),
// .write_en (ctrl_reg_write_en),
// .wdata (csr_reg_wdata),
// .rdata (csr_reg_rdata),
// // Data Transfer Request Signaling
// .req_act_ch0 (in_dma_req_act),
// .req_act_ch1 (out_dma_req_act),
// .req_act_ch2 (1'b0),
// .req_act_ch3 (1'b0),
// .req_act_ch4 (1'b0),
// // DMA Request Output
// .drq_ch0 (in_data_req),
// .drq_ch1 (out_data_req),
// .drq_ch2 (),
// .drq_ch3 (),
// .drq_ch4 (),
// // Interrupt Request Output
// .irq_ch0 (),
// .irq_ch1 (),
// .irq_ch2 (),
// .irq_ch3 (),
// .irq_ch4 (),
// .irq_merged ()
// );
//**********************************************************
// Accelerator Engine
......
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