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SOC1-167: Updated Filelists and created a system filelist to build system including accelerator

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cmsdk/ip/cmsdk_ahb_default_slave.v deleted 100644 → 0
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− 141
View file @ cbeeec65
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : AHB-Lite Default Slave
//-----------------------------------------------------------------------------
//
// Returns an error response when selected for a transfer
//
module cmsdk_ahb_default_slave (
// Inputs
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Slave select
input wire [1:0] HTRANS, // Transfer type
input wire HREADY, // System ready
// Outputs
output wire HREADYOUT, // Slave ready
output wire HRESP); // Slave response
//
// Start of main code
//
// Internal signals
wire trans_req; // Transfer Request
reg [1:0] resp_state; // Current FSM state for two-cycle error response
wire [1:0] next_state; // Next FSM state
// Transfer address phase completes
assign trans_req = HSEL & HTRANS[1] & HREADY;
// Generate next state for the FSM.
// Bit 0 is connected to HREADYOUT and bit 1 is connected to HRESP,
// so the state encodings are:
// 01 - Idle
// 10 - 1st cycle of error response
// 11 - 2nd cycle of error response
assign next_state = { trans_req | (~resp_state[0]),
~trans_req };
// Registering FSM state
always @(posedge HCLK or negedge HRESETn)
if (~HRESETn)
resp_state <= 2'b01; // ensure HREADYOUT is HIGH at reset
else
resp_state <= next_state;
// Connect to output
assign HREADYOUT = resp_state[0];
assign HRESP = resp_state[1];
`ifdef ARM_AHB_ASSERT_ON
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
`include "std_ovl_defines.h"
reg ovl_last_hreadyout;
reg ovl_last_hsel;
reg [1:0] ovl_last_htrans;
reg ovl_last_hready;
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
ovl_last_hreadyout <= 1'b1;
ovl_last_hsel <= 1'b0;
ovl_last_htrans <= 2'b00;
ovl_last_hready <= 1'b1;
end
else
begin
ovl_last_hreadyout <= HREADYOUT;
ovl_last_hsel <= HSEL;
ovl_last_htrans <= HTRANS;
ovl_last_hready <= HREADY;
end
end
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If HREADYOUT is 0, HRESP must be high")
u_ovl_error_response_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~HREADYOUT),
.consequent_expr(HRESP)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If in last cycle HREADYOUT is 0, this cycle both HRESP and HREADYOUT")
u_ovl_error_response_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~ovl_last_hreadyout),
.consequent_expr(HRESP & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is not selected, or if transfer is idle/busy, response must be OKAY")
u_ovl_error_fault_check_1
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(~(ovl_last_hsel & ovl_last_htrans[1]) & ovl_last_hready),
.consequent_expr((~HRESP) & HREADYOUT)
);
assert_implication
#(`OVL_ERROR,`OVL_ASSERT,
"If device is selected, and if transfer is nseq/seq, response must be ERROR")
u_ovl_error_fault_check_2
(.clk(HCLK), .reset_n(HRESETn),
.antecedent_expr(ovl_last_hsel & ovl_last_htrans[1] & ovl_last_hready),
.consequent_expr(HRESP & (~HREADYOUT))
);
`endif
endmodule
cmsdk/ip/cmsdk_ahb_ram_beh.v deleted 100644 → 0
+ 0
− 209
View file @ cbeeec65
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple AHB RAM behavioral model
//-----------------------------------------------------------------------------
module cmsdk_ahb_ram_beh #(
parameter AW = 16,// Address width
parameter filename = "",
parameter WS_N = 0, // First access wait state
parameter WS_S = 0) // Subsequent access wait state
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HSEL, // Device select
input wire [AW-1:0] HADDR, // Address
input wire [1:0] HTRANS, // Transfer control
input wire [2:0] HSIZE, // Transfer size
input wire HWRITE, // Write control
input wire [31:0] HWDATA, // Write data
input wire HREADY, // Transfer phase done
output wire HREADYOUT, // Device ready
output wire [31:0] HRDATA, // Read data output
output wire HRESP); // Device response (always OKAY)
// Internal signals
reg [7:0] ram_data[0:((1<<AW)-1)]; // 64k byte of RAM data
wire read_valid; // Address phase read valid
wire write_valid; // Address phase write valid
reg read_enable; // Data phase read enable
reg write_enable; // Data phase write enable
reg [3:0] reg_byte_lane; // Data phase byte lane
reg [3:0] next_byte_lane; // Next state of reg_byte_lane
reg [7:0] rdata_out_0; // Read Data Output byte#0
reg [7:0] rdata_out_1; // Read Data Output byte#1
reg [7:0] rdata_out_2; // Read Data Output byte#2
reg [7:0] rdata_out_3; // Read Data Output byte#3
reg [AW-1:0] word_addr; // Word aligned address
wire [AW-1:0] nxt_word_addr; // Word aligned address
integer i; // Loop counter
// Wait state control
wire [31:0] nxt_waitstate_cnt;
reg [31:0] reg_waitstate_cnt;
wire sequential_access;
// Start of main code
// Initialize ROM
initial
begin
for (i=0;i<(1<<AW);i=i+1)
begin
ram_data[i] = 8'h00; //Initialize all data to 0
end
if (filename != "")
begin
$readmemh(filename, ram_data); // Then read in program code
end
end
// Generate read control (address phase)
assign read_valid = HSEL & HREADY & HTRANS[1] & (~HWRITE);
// Generate write control (address phase)
assign write_valid = HSEL & HREADY & HTRANS[1] & HWRITE;
// Read enable for each byte (address phase)
always @(read_valid or write_valid or HADDR or HSIZE)
begin
if (read_valid | write_valid)
begin
case (HSIZE)
0 : // Byte
begin
case (HADDR[1:0])
0: next_byte_lane = 4'b0001; // Byte 0
1: next_byte_lane = 4'b0010; // Byte 1
2: next_byte_lane = 4'b0100; // Byte 2
3: next_byte_lane = 4'b1000; // Byte 3
default:next_byte_lane = 4'b0000; // Address not valid
endcase
end
1 : // Halfword
begin
if (HADDR[1])
next_byte_lane = 4'b1100; // Upper halfword
else
next_byte_lane = 4'b0011; // Lower halfword
end
default : // Word
next_byte_lane = 4'b1111; // Whole word
endcase
end
else
next_byte_lane = 4'b0000; // Not reading
end
// Registering control signals to data phase
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
begin
reg_byte_lane <= 4'b0000;
read_enable <= 1'b0;
write_enable <= 1'b0;
word_addr <= {AW{1'b0}};
end
else if (HREADY)
begin
reg_byte_lane <= next_byte_lane;
read_enable <= read_valid;
write_enable <= write_valid;
word_addr <= nxt_word_addr;
end
end
assign nxt_word_addr = {HADDR[AW-1:2], 2'b00};
// Read operation
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[0]))
rdata_out_0 = ram_data[word_addr ];
else
rdata_out_0 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[1]))
rdata_out_1 = ram_data[word_addr+1];
else
rdata_out_1 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[2]))
rdata_out_2 = ram_data[word_addr+2];
else
rdata_out_2 = 8'h00;
always @(read_enable or reg_byte_lane or word_addr)
if ((read_enable & reg_byte_lane[3]))
rdata_out_3 = ram_data[word_addr+3];
else
rdata_out_3 = 8'h00;
// Registered write
always @(posedge HCLK)
begin
if (write_enable & reg_byte_lane[0])
begin
ram_data[word_addr ] = HWDATA[ 7: 0];
end
if (write_enable & reg_byte_lane[1])
begin
ram_data[word_addr+1] = HWDATA[15: 8];
end
if (write_enable & reg_byte_lane[2])
begin
ram_data[word_addr+2] = HWDATA[23:16];
end
if (write_enable & reg_byte_lane[3])
begin
ram_data[word_addr+3] = HWDATA[31:24];
end
end
// Wait state control
// Wait state generate treat access as sequential if
// HTRANS = 2'b11, or access address is in the same word,
// or if the access is in the next word
assign sequential_access = (HTRANS==2'b11) |
(HADDR[AW-1:2] == word_addr[AW-1:2]) |
(HADDR[AW-1:2] == (word_addr[AW-1:2]+1));
assign nxt_waitstate_cnt = (read_valid|write_valid) ?
((sequential_access) ? WS_S : WS_N) :
((reg_waitstate_cnt!=0) ? (reg_waitstate_cnt - 1) : 0);
// Register wait state counter
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_waitstate_cnt <= 0;
else
reg_waitstate_cnt <= nxt_waitstate_cnt;
end
// Connect to top level
assign HREADYOUT = (reg_waitstate_cnt==0) ? 1'b1 : 1'b0;
assign HRESP = 1'b0; // Always response with OKAY
// Read data output
assign HRDATA = {rdata_out_3, rdata_out_2, rdata_out_1,rdata_out_0};
endmodule
cmsdk/ip/cmsdk_ahb_slave_mux.v deleted 100644 → 0
+ 0
− 226
View file @ cbeeec65
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Simple AHB slave multiplexer
//-----------------------------------------------------------------------------
// Each port can be disabled by parameter if not used.
module cmsdk_ahb_slave_mux #(
// Parameters to enable/disable ports
// By default all ports are enabled
parameter PORT0_ENABLE=1,
parameter PORT1_ENABLE=1,
parameter PORT2_ENABLE=1,
parameter PORT3_ENABLE=1,
parameter PORT4_ENABLE=1,
parameter PORT5_ENABLE=1,
parameter PORT6_ENABLE=1,
parameter PORT7_ENABLE=1,
parameter PORT8_ENABLE=1,
parameter PORT9_ENABLE=1,
// Data Bus Width
parameter DW=32
)
(
input wire HCLK, // Clock
input wire HRESETn, // Reset
input wire HREADY, // Bus ready
input wire HSEL0, // HSEL for AHB Slave #0
input wire HREADYOUT0, // HREADY for Slave connection #0
input wire HRESP0, // HRESP for slave connection #0
input wire [DW-1:0] HRDATA0, // HRDATA for slave connection #0
input wire HSEL1, // HSEL for AHB Slave #1
input wire HREADYOUT1, // HREADY for Slave connection #1
input wire HRESP1, // HRESP for slave connection #1
input wire [DW-1:0] HRDATA1, // HRDATA for slave connection #1
input wire HSEL2, // HSEL for AHB Slave #2
input wire HREADYOUT2, // HREADY for Slave connection #2
input wire HRESP2, // HRESP for slave connection #2
input wire [DW-1:0] HRDATA2, // HRDATA for slave connection #2
input wire HSEL3, // HSEL for AHB Slave #3
input wire HREADYOUT3, // HREADY for Slave connection #3
input wire HRESP3, // HRESP for slave connection #3
input wire [DW-1:0] HRDATA3, // HRDATA for slave connection #3
input wire HSEL4, // HSEL for AHB Slave #4
input wire HREADYOUT4, // HREADY for Slave connection #4
input wire HRESP4, // HRESP for slave connection #4
input wire [DW-1:0] HRDATA4, // HRDATA for slave connection #4
input wire HSEL5, // HSEL for AHB Slave #5
input wire HREADYOUT5, // HREADY for Slave connection #5
input wire HRESP5, // HRESP for slave connection #5
input wire [DW-1:0] HRDATA5, // HRDATA for slave connection #5
input wire HSEL6, // HSEL for AHB Slave #6
input wire HREADYOUT6, // HREADY for Slave connection #6
input wire HRESP6, // HRESP for slave connection #6
input wire [DW-1:0] HRDATA6, // HRDATA for slave connection #6
input wire HSEL7, // HSEL for AHB Slave #7
input wire HREADYOUT7, // HREADY for Slave connection #7
input wire HRESP7, // HRESP for slave connection #7
input wire [DW-1:0] HRDATA7, // HRDATA for slave connection #7
input wire HSEL8, // HSEL for AHB Slave #8
input wire HREADYOUT8, // HREADY for Slave connection #8
input wire HRESP8, // HRESP for slave connection #8
input wire [DW-1:0] HRDATA8, // HRDATA for slave connection #8
input wire HSEL9, // HSEL for AHB Slave #9
input wire HREADYOUT9, // HREADY for Slave connection #9
input wire HRESP9, // HRESP for slave connection #9
input wire [DW-1:0] HRDATA9, // HRDATA for slave connection #9
output wire HREADYOUT, // HREADY output to AHB master and AHB slaves
output wire HRESP, // HRESP to AHB master
output wire [DW-1:0] HRDATA // Read data to AHB master
);
wire mux_hready; // multiplexed HREADY sigal
reg [9:0] reg_hsel; // Register selection control
wire [9:0] nxt_hsel_reg; // next state for nxt_hsel_reg
assign nxt_hsel_reg[0] = HSEL0 & (PORT0_ENABLE!=0);
assign nxt_hsel_reg[1] = HSEL1 & (PORT1_ENABLE!=0);
assign nxt_hsel_reg[2] = HSEL2 & (PORT2_ENABLE!=0);
assign nxt_hsel_reg[3] = HSEL3 & (PORT3_ENABLE!=0);
assign nxt_hsel_reg[4] = HSEL4 & (PORT4_ENABLE!=0);
assign nxt_hsel_reg[5] = HSEL5 & (PORT5_ENABLE!=0);
assign nxt_hsel_reg[6] = HSEL6 & (PORT6_ENABLE!=0);
assign nxt_hsel_reg[7] = HSEL7 & (PORT7_ENABLE!=0);
assign nxt_hsel_reg[8] = HSEL8 & (PORT8_ENABLE!=0);
assign nxt_hsel_reg[9] = HSEL9 & (PORT9_ENABLE!=0);
// Registering MuxCtrl
always @(posedge HCLK or negedge HRESETn)
begin
if (~HRESETn)
reg_hsel <= {10{1'b0}};
else if (HREADY) // advance pipeline if HREADY is 1
reg_hsel <= nxt_hsel_reg;
end
assign mux_hready =
((~reg_hsel[0]) | HREADYOUT0 | (PORT0_ENABLE==0)) &
((~reg_hsel[1]) | HREADYOUT1 | (PORT1_ENABLE==0)) &
((~reg_hsel[2]) | HREADYOUT2 | (PORT2_ENABLE==0)) &
((~reg_hsel[3]) | HREADYOUT3 | (PORT3_ENABLE==0)) &
((~reg_hsel[4]) | HREADYOUT4 | (PORT4_ENABLE==0)) &
((~reg_hsel[5]) | HREADYOUT5 | (PORT5_ENABLE==0)) &
((~reg_hsel[6]) | HREADYOUT6 | (PORT6_ENABLE==0)) &
((~reg_hsel[7]) | HREADYOUT7 | (PORT7_ENABLE==0)) &
((~reg_hsel[8]) | HREADYOUT8 | (PORT8_ENABLE==0)) &
((~reg_hsel[9]) | HREADYOUT9 | (PORT9_ENABLE==0)) ;
assign HREADYOUT = mux_hready; // Connect to top level
assign HRDATA =
({DW{(reg_hsel[0] & (PORT0_ENABLE!=0))}} & HRDATA0) |
({DW{(reg_hsel[1] & (PORT1_ENABLE!=0))}} & HRDATA1) |
({DW{(reg_hsel[2] & (PORT2_ENABLE!=0))}} & HRDATA2) |
({DW{(reg_hsel[3] & (PORT3_ENABLE!=0))}} & HRDATA3) |
({DW{(reg_hsel[4] & (PORT4_ENABLE!=0))}} & HRDATA4) |
({DW{(reg_hsel[5] & (PORT5_ENABLE!=0))}} & HRDATA5) |
({DW{(reg_hsel[6] & (PORT6_ENABLE!=0))}} & HRDATA6) |
({DW{(reg_hsel[7] & (PORT7_ENABLE!=0))}} & HRDATA7) |
({DW{(reg_hsel[8] & (PORT8_ENABLE!=0))}} & HRDATA8) |
({DW{(reg_hsel[9] & (PORT9_ENABLE!=0))}} & HRDATA9) ;
assign HRESP =
(reg_hsel[0] & HRESP0 & (PORT0_ENABLE!=0)) |
(reg_hsel[1] & HRESP1 & (PORT1_ENABLE!=0)) |
(reg_hsel[2] & HRESP2 & (PORT2_ENABLE!=0)) |
(reg_hsel[3] & HRESP3 & (PORT3_ENABLE!=0)) |
(reg_hsel[4] & HRESP4 & (PORT4_ENABLE!=0)) |
(reg_hsel[5] & HRESP5 & (PORT5_ENABLE!=0)) |
(reg_hsel[6] & HRESP6 & (PORT6_ENABLE!=0)) |
(reg_hsel[7] & HRESP7 & (PORT7_ENABLE!=0)) |
(reg_hsel[8] & HRESP8 & (PORT8_ENABLE!=0)) |
(reg_hsel[9] & HRESP9 & (PORT9_ENABLE!=0)) ;
// ------------------------------------------------------------
`ifdef ARM_AHB_ASSERT_ON
// ------------------------------------------------------------
// Assertions
// ------------------------------------------------------------
`include "std_ovl_defines.h"
// When HREADYOUT is low, reg_hsel must be non-zero (Property of design)
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"reg_hsel must not be zero when HREADYOUT is low")
u_ovl_readyout_asserted_when_not_active
(.clk(HCLK), .reset_n(HRESETn),
.test_expr( (~HREADYOUT) & (reg_hsel=={10{1'b0}}))
);
// Properties of the inputs of the design
// HSEL should be one-hot
// If this OVL fires - there is an error in the design of the address decoder
assert_zero_one_hot
#(`OVL_FATAL,10,`OVL_ASSERT,
"Only one HSEL input can be activated.")
u_ovl_hsel_one_hot
(.clk(HCLK), .reset_n(HRESETn),
.test_expr({HSEL0,
HSEL1,
HSEL2,
HSEL3,
HSEL4,
HSEL5,
HSEL6,
HSEL7,
HSEL8,
HSEL9}));
// When HREADYOUT is low, HREADY should be low
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"HREADY should be low when HREADYOUT is low")
u_ovl_ready_mismatch
(.clk(HCLK), .reset_n(HRESETn),
.test_expr( (~HREADYOUT) & HREADY )
);
// Check if a disabled port is selected
// (system design error, check the verilog parameter in module instantiation)
assert_never
#(`OVL_ERROR,`OVL_ASSERT,
"A disabled port is selected")
u_ovl_disabled_port_selected
(.clk(HCLK), .reset_n(HRESETn),
.test_expr(HREADY & (
((PORT0_ENABLE==0) & HSEL0) |
((PORT1_ENABLE==0) & HSEL1) |
((PORT2_ENABLE==0) & HSEL2) |
((PORT3_ENABLE==0) & HSEL3) |
((PORT4_ENABLE==0) & HSEL4) |
((PORT5_ENABLE==0) & HSEL5) |
((PORT6_ENABLE==0) & HSEL6) |
((PORT7_ENABLE==0) & HSEL7) |
((PORT8_ENABLE==0) & HSEL8) |
((PORT9_ENABLE==0) & HSEL9)
))
);
`endif
endmodule
cmsdk/vip/cmsdk_ahb_fileread_funnel.v deleted 100644 → 0
+ 0
− 90
View file @ cbeeec65
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Convert 64-bit bus from ahb_fileread_core to 32-bit
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : A data bus multiplexor, used to connect a 32 bit slave
// to a 64 bit bus.
// Supports transfers up to 32 bit in size.
// --========================================================================--
module cmsdk_ahb_fileread_funnel (
// Clock and Reset
input wire HCLK,
input wire HRESETn,
// Interface to AHB
input wire HADDR2S,
input wire [63:0] HWDATAS,
input wire HREADYS,
output wire [63:0] HRDATAS,
// Interface to slave
output reg [31:0] HWDATAM,
input wire [31:0] HRDATAM);
// -----------------------------------------------------------------------------
// Signal Declarations
// -----------------------------------------------------------------------------
reg haddr2s_reg; // Delayed version of address bit2
// =============================================================================
// Beginning of main verilog code
// =============================================================================
//------------------------------------------------------------------------------
// Generate Delayed version of HADDR2S
//------------------------------------------------------------------------------
always@(posedge HCLK or negedge HRESETn)
begin : p_haddr2s_reg
if (HRESETn == 1'b0)
haddr2s_reg <= 1'b0;
else
begin
if (HREADYS == 1'b1)
haddr2s_reg <= HADDR2S;
end
end // block: p_haddr2s_reg
// -----------------------------------------------------------------------------
// Write Data MUX
// -----------------------------------------------------------------------------
// Note: To support Big-Endian systems the polarity of the HWDATAM MUX should be
// reversed.
always@(haddr2s_reg or HWDATAS)
begin : p_write_mux
if (haddr2s_reg == 1'b0)
HWDATAM = HWDATAS[31:0];
else
HWDATAM = HWDATAS[63:32];
end // block: p_write_mux
// -----------------------------------------------------------------------------
// Read Data bus
// -----------------------------------------------------------------------------
assign HRDATAS = {HRDATAM,HRDATAM};
endmodule
// --================================= End ===================================--
cmsdk/vip/cmsdk_ahb_fileread_master32.v deleted 100644 → 0
+ 0
− 134
View file @ cbeeec65
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : 32-bit AHB File Reader Bus Master
//-----------------------------------------------------------------------------
// ----------------------------------------------------------------------------
// Purpose : This entity ties together the sub blocks that
// form the 32-bit File Reader Bus Master, namely an
// AHB-Lite File Reader Core and a bus funnel .
// --========================================================================--
// Note
// This top level file converts AHB Lite extension
// signals in ARM1136 to sideband signals used in
// Cortex-M3/M4
// --========================================================================--
module cmsdk_ahb_fileread_master32 #(
parameter InputFileName = "filestim.m2d", // stimulus data file name
parameter MessageTag = "FileReader:", // tag on each FileReader message
parameter StimArraySize = 5000) // stimulus data array size:
// should be large enough to hold
// entire stimulus data file
(
// system ports
input wire HCLK, // system clock
input wire HRESETn, // system reset
// AHB ports
input wire HREADY, // slave ready signal
input wire HRESP, // slave response bus
input wire [31:0] HRDATA, // data, slave to master
input wire EXRESP, // Exclusive response (tie low if not used)
output wire [1:0] HTRANS, // transfer type
output wire [2:0] HBURST, // burst type
output wire [3:0] HPROT, // transfer protection
output wire EXREQ, // Exclusive access request
output wire [1:0] MEMATTR, // Memory attribute
output wire [2:0] HSIZE, // transfer size
output wire HWRITE, // transfer direction
output wire HMASTLOCK, // transfer is locked
output wire [31:0] HADDR, // transfer address
output wire [31:0] HWDATA, // data, master to slave
output wire [31:0] LINENUM); // line number in stimulus file
// Internal AHB-Lite Bus Signals
wire [2:0] hresp_core; // slave response
wire [63:0] hrdata_core; // data from slave to master
wire [31:0] haddr_core; // transfer address
wire [63:0] hwdata_core; // data from master to slave
wire [5:0] hprot_core; // transfer protection
//------------------------------------------------------------------------------
// structural
//------------------------------------------------------------------------------
// Instance of AHB-Lite File Reader connected to internal AHB-Lite system
cmsdk_ahb_filereadcore
#(.input_filename(InputFileName),
.message_tag(MessageTag),
.stim_array_size(StimArraySize))
u_ahb_filereadcore (
.HCLK (HCLK),
.HRESETn (HRESETn),
.HREADY (HREADY),
.HRESP (hresp_core),
.HRDATA (hrdata_core),
.HTRANS (HTRANS),
.HBURST (HBURST),
.HPROT (hprot_core),
.HSIZE (HSIZE),
.HWRITE (HWRITE),
.HMASTLOCK (HMASTLOCK),
.HADDR (haddr_core),
.HWDATA (hwdata_core),
.HUNALIGN (),
.HBSTRB (),
.LINENUM (LINENUM)
);
// Instance of a Funnel to translate the 64-bit AHB-Lite data bus to 32-bit.
cmsdk_ahb_fileread_funnel u_ahb_fileread_funnel (
.HCLK (HCLK),
.HRESETn (HRESETn),
// 64-bit interface to AHB
.HREADYS (HREADY),
.HADDR2S (haddr_core[2]),
.HWDATAS (hwdata_core),
.HRDATAS (hrdata_core),
// 32-bit interface to slave
.HWDATAM (HWDATA),
.HRDATAM (HRDATA)
);
// Convert internal versions of port signals
assign HADDR = haddr_core; // Drive port with internal signal
assign HPROT = hprot_core[3:0];
assign EXREQ = hprot_core[5];
assign MEMATTR = {1'b0, hprot_core[4]};
assign hresp_core = {EXRESP, 1'b0,HRESP}; // Drive unused bit of hresp_core
endmodule
// --================================ End ==================================--
cmsdk/vip/cmsdk_ahb_filereadcore.v deleted 100644 → 0
+ 0
− 1488
View file @ cbeeec65
This diff is collapsed.
flist/ahb/ahb_ip.flist
+ 4
− 5
View file @ 1cb75f46
......@@ -16,9 +16,8 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/cmsdk/ip/
+incdir+$(PROJECT_DIR)/hdl/ip/
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
$(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_default_slave.v
$(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_slave_mux.v
// $(PROJECT_DIR)/cmsdk/ip/cmsdk_ahb_ram_beh.v
\ No newline at end of file
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_slave_mux/verilog
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_default_slave/verilog
\ No newline at end of file
flist/ahb/ahb_vip.flist
+ 2
− 5
View file @ 1cb75f46
......@@ -16,9 +16,6 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/cmsdk/vip/
+incdir+$(PROJECT_DIR)/cmsdk/vip/
+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/msdk_ahb_fileread_masters/verilog
$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_fileread_master32.v
$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_fileread_funnel.v
$(PROJECT_DIR)/cmsdk/vip/cmsdk_ahb_filereadcore.v
\ No newline at end of file
-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/msdk_ahb_fileread_masters/verilog
flist/nanosoc/nanosoc_vip.flist → flist/nanosoc/nanosoc_tb.flist
+ 0
− 0
View file @ 1cb75f46
File moved
flist/project/system.flist
+ 38
− 2
View file @ 1cb75f46
......@@ -16,7 +16,43 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/system/src/
+incdir+$(PROJECT_DIR)/system/src/
-f $(PROJECT_DIR)/flist/project/secworks_sha256_stream.flist
// ============= Wrapper Filelist =========================
-f $(PROJECT_DIR)/flist/project/wrapper.flist
// ============= System Component Filelist ================
// - CMSDK IP
-f $(PROJECT_DIR)/flist/ahb/ahb_ip.flist
-f $(PROJECT_DIR)/flist/apb/apb_ip.flist
// - Top level
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
// - NanoSoC Bus Matrix
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
// - Generic Pad Library
-f $(PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
// - CMSDK VIP
-f $(PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist
// - Corstone-101 System components
-f $(PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
// - DMA controller
-f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
// - Debug Controllers
-f $(PROJECT_DIR)/flist/debug/usrt_ip.flist
-f $(PROJECT_DIR)/flist/debug/adp-control_ip.flist
-f $(PROJECT_DIR)/flist/debug/ft1248_vip.flist
// - Cortex-M0 IP
-f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
// - NanoSoC Custom Expansion Region
$(PROJECT_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file
nanosoc @ 0dd20509
Compare e63f4b85...0dd20509
Subproject commit e63f4b85974feff6ea93e768c78a4a479f60b513
Subproject commit 0dd2050946f895436ac9af62a23054b0584f8d7f
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