SOC1-167: Updated filelists to point to new nanosoc locations

flist/nanosoc/nanosoc_chip_ip.flist

@@ -16,18 +16,21 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_chip.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_chip_pads.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
 
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_cpu.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_sysio.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/nanosoc_sys_ahb_decode.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
 
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_ahb_cs_rom_table.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_pin_mux.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_stclkctrl.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_clkctrl.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_mcu_sysctrl.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
 
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/bootrom.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ahb_bootrom.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
+
+
+$(NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file

flist/nanosoc/nanosoc_matrix_ip.flist

@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
++incdir+$(NANOSOC_TECH_DIR)/system/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
 
--y $(NANOSOC_TECH_DIR)/systems/nanososc/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
\ No newline at end of file
+-y $(NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrixgen_ahb_busmatrix/verilog/built/soclabs_ahb32_4x7_busmatrix
\ No newline at end of file

flist/nanosoc/nanosoc_tb.flist

@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    DMA-230 search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/
++incdir+$(NANOSOC_TECH_DIR)/system/verilog/
 
 // - Top-level testbench
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/tb_nanosoc.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
 
 // - Testbench components
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_clkreset.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_uart_capture.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/axi_stream_io_8_txd_from_file.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ft1248x1_to_axi_streamio_v1_0.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/axi_stream_io_8_rxd_to_file.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/track_tb_iostream.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/dma_log_to_file.v
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/aes128_log_to_file.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
+
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file

flist/nanosoc/nanosoc_test_io_ip.flist

@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Chip Test Interface IP Filelists   =============
--f $(PROJECT_DIR)/flist/test_io/adp-control_ip.flist
--f $(PROJECT_DIR)/flist/test_io/ft1248_ip.flist
--f $(PROJECT_DIR)/flist/test_io/usrt_ip.flist
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
+$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
+$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
\ No newline at end of file

flist/test_io/adp-control_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC ADP Control Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for ADP Control IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    ADP Control search path    =============
-$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPcontrol_v1_0.v
-$(NANOSOC_TECH_DIR)/test_io/adp_control/verilog/ADPmanager.v
\ No newline at end of file

flist/test_io/ft1248_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC FT1248 VIP Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for FT1248 IO VIP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============    FT1248 VIP search path    =============
-$(NANOSOC_TECH_DIR)/test_io/ft1248_stream_io/verilog/ft1248_stream_io_v1_0.v
\ No newline at end of file

flist/test_io/usrt_ip.flist

-//-----------------------------------------------------------------------------
-// NanoSoC APB USRT Control Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for APB USRT IP
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// =============   APB USRT search path    =============
-$(NANOSOC_TECH_DIR)/systems/nanososc/verilog/cmsdk_apb_usrt.v
\ No newline at end of file

nanosoc @ 8f599dbb

-Subproject commit ab2f30d5531ee4ea52b932317b5c223800c84798
+Subproject commit 8f599dbbb64ba2b39beea654dd211d7743f89f64

simulate/socsim/system_secworks_sha256.sh

@@ -24,7 +24,7 @@ cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
 echo ${2}
-make -C $NANOSOC_TECH_DIR/systems/mcu run_xm \
+make -C $NANOSOC_TECH_DIR/system run_xm \
     SIM_DIR=$SIM_DIR \
     ADP_FILE=$PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
     ${@:2}