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Commit 068bb6df authored by dam1n19's avatar dam1n19
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SOC1-208: Added top-level module comments to filelist

parent 004792a4
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...@@ -2,7 +2,8 @@ ...@@ -2,7 +2,8 @@
*.vvp *.vvp
simulate/sim/* simulate/sim/*
.socinit .socinit
wrapper/html accelerator/html/*
system/bootrom wrapper/html/*
system/html system/src/bootrom
system/html/*
flist/tmp flist/tmp
\ No newline at end of file
...@@ -6,6 +6,8 @@ ...@@ -6,6 +6,8 @@
// your accelerator. // your accelerator.
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// DESIGN_TOP accelerator
// ============= Verilog library extensions =========== // ============= Verilog library extensions ===========
+libext+.v+.vlib +libext+.v+.vlib
......
...@@ -12,6 +12,8 @@ ...@@ -12,6 +12,8 @@
// Abstract : Verilog Command File for Top-level Accelerator System // Abstract : Verilog Command File for Top-level Accelerator System
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// DESIGN_TOP nanosoc_chip
// ============= Verilog library extensions =========== // ============= Verilog library extensions ===========
+libext+.v+.vlib +libext+.v+.vlib
......
...@@ -12,6 +12,8 @@ ...@@ -12,6 +12,8 @@
// Abstract : Verilog Command File for Top-level Accelerator Wrapper // Abstract : Verilog Command File for Top-level Accelerator Wrapper
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
// DESIGN_TOP your_wrapper
// ============= Verilog library extensions =========== // ============= Verilog library extensions ===========
+libext+.v+.vlib +libext+.v+.vlib
......
Subproject commit 7118711fe3f7fc93ad65bcd46203de73358b0545 Subproject commit fa8ca0c8eb2480ca259530dca416776a1923b73a
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