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Created with Raphaël 2.2.08Apr747Mar63Feb28Jan2116Dec1512330Nov28191514729Oct288743228Sep27262518171230Aug232215917Jul315Jun23May222111Mar21Feb1952122Jan16151211108719Dec151265430Nov21625Oct1243229Sep28272622211918151424Aug211419Jul1210765432130Jun292826232221201916151413643127May262218171615121143230Apr292827262524222120181711331Mar30292826221918151428Feb2726232221201512add programmable prescalar to FT1248 interface and boot/stdout init code for div 16 (resets to div 256)mainmainreplace the alt-function P0/1 multiplexing to repair failing peripheral testsadd dma230 support and tests to dataio functionalityfeat_dma230_dat…feat_dma230_dataioAdd TSMC 16nm initial flowIntegrate AHB XiP QSPI into nanosocfeat_qspi_romfeat_qspi_romaugment busmatrix for EXTROM (ready for QSPI) region 0x1800000 (and 0x00000000 remap[1])optimize arbitration history statefix a synthesis error in latest extio8x4_ifsmupgrade extio8x4 arbitrationadd extio data channels to QuickStart testbenchremove uart1 from interrupt_demo testsnew dataio channel testbench extension and testcodeUpdate docs for EXP Sram preloadAdd memory preload for EXP rams in simulationDoc update add initial info on sims and fpgaupdate boot-ROM startup code for 2024 nanosocupdate boot-ROM startup message for 2024 nanosocextio synchronizers reset high to suppress spurious requestsand finalize kria kr260 FPGA target building correctlyfinally get kria kv260 FPGA target building correctlyrepair the kria board/device parametersUpdate DocsInitial Add datasheet tex and make targetAdd synopsys 28nm SLM git to socpullupdate vivado pinmap pullups across zynq platformsupdate vivado nanosoc_design scripts for 2024_1 (and 2021_1) versionsSeperate flist for FPGA and behavioural28nm nanosoc flow update, still under developmentsupport FPGA targets other than zynqplusupdate FPGA targets for extio commsupdate and simplify zcu104 extio validation to 40MHzupdate the FPGA top level for extio controllerupdate the FPGA IP components for extio controllerzcu104 target extio testbenchfix up QuickStart testbench for extio validationfix up QuickStart extio flistfix up QuickStart tb fileistexclude uart tests while getting extio validatedexclude uart tests while getting extio validatedmerge extio8x4 interface and tests