makefile

@@ -27,6 +27,8 @@ QUICKSTART ?= no
 
 ASIC ?= no
 
+FAST_SIM ?= yes
+
 #-------------------------------------
 # - Directory Setups
 #-------------------------------------
@@ -65,6 +67,11 @@ ifeq ($(ACCELERATOR),yes)
 	NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
 endif
 
+ifeq ($(FAST_SIM),yes)
+	DEFINES_VC += +define+FAST_SIM
+	NANOSOC_DEFINES += FAST_SIM
+endif
+
 # System Design Filelist
 ifeq ($(QUICKSTART),yes)
 	DESIGN_VC            ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist

verif/tb/verilog/nanosoc_tb.v

@@ -319,9 +319,16 @@ reg baud_clk_del;
   wire rxd8_tvalid;
   wire [7:0] rxd8_tdata ;
 
+`ifdef FAST_SIM
+  parameter FAST_LOAD = 1;
+`else
+  parameter FAST_LOAD = 0;
+`endif
+
 `ifndef COCOTB_SIM
   nanosoc_axi_stream_io_8_txd_from_file #(
-    .TXDFILENAME(ADP_FILENAME)
+    .TXDFILENAME(ADP_FILENAME),
+    .FAST_LOAD(FAST_LOAD)
   ) u_nanosoc_axi_stream_io_8_txd_from_file (
     .aclk       (CLK),
     .aresetn    (NRST),