flist/corstone101_ip.flist

@@ -18,7 +18,7 @@
 // =============    Corstone-101 search path    =============
 +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_dualtimers/verilog
 +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_watchdog/verilog
-+incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
++incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories
 
 // CMSDK APB Timer IP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_apb_timer/verilog
@@ -74,7 +74,7 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_iop_gpio/verilog/cmsdk_
 $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/clkgate/cmsdk_clock_gate.v
 
 // CMSDK Memory Models
-//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/
+//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories
 $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram_beh.v
 $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_ram.v
 $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_ahb_rom.v
@@ -87,4 +87,4 @@ $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/memories/cmsdk_sram256
 
 // CMSDK AHB to SRAM bridge IP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
\ No newline at end of file
+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v

flist/corstone101_vip.flist

@@ -21,15 +21,15 @@
 +incdir+$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
 
 // CMSDK Debug Tester VIP
-//-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v
+-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_ahb_interconnect.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester_trace_capture.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/cmsdk_debug_tester/verilog/cmsdk_debug_tester.v
 
 // CMSDK AHB Lite Protocol Checker VIP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog
-$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v
 
 // CMSDK APB Protocol Checker VIP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog
-// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v
\ No newline at end of file
+// $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v

flist/corstone101_vip_qs.flist

@@ -28,8 +28,8 @@ $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/cmsdk_debug_test
 
 // CMSDK AHB Lite Protocol Checker VIP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog
-$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v
+//$(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/AhbLitePC/verilog/AhbLitePC.v
 
 // CMSDK APB Protocol Checker VIP
 //-y $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog
-// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v
\ No newline at end of file
+// $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0-QS/Corstone-101-logical/models/protocol_checkers/ApbPC/verilog/ApbPC.v

sldma230_tech @ 0f0bf3de

-Subproject commit e4ebbf3c9d46d56cb76b2627a18c2f019c44abd7
+Subproject commit 0f0bf3dee094e9e6801210c1d5f190dea912395d

software/common/validation/apb_mux_tests.c

@@ -124,14 +124,14 @@ int main (void)
     if ( ID_Check(&blank_id[0],         0x4000A000          ) == 1 ) err_code |= 1<<10;
   puts ("11: APB test slave");
     if ( APB_test_slave_Check(          0x4000B000          ) == 1 ) err_code |= 1<<11;
-  puts ("12: DMAC 1 (Not Implemented) - Slave Error");
-    if ( ID_Check(&blank_id[0],         0x4000C000          ) == 1 ) err_code |= 1<<12;
+  //puts ("12: DMAC 1 (Not Implemented) - Slave Error");
+  //  if ( ID_Check(&blank_id[0],         0x4000C000          ) == 1 ) err_code |= 1<<12;
   puts ("13: blank - default slave (generates slave error)");
     if ( ID_Check(&blank_id[0],         0x4000D000          ) == 1 ) err_code |= 1<<13;
   puts ("14: Debug USRT");
     if ( ID_Check(&apb_uart_id[0],      CMSDK_USRT2_BASE    ) == 1 ) err_code |= 1<<14;
-  puts ("15: DMAC 0 (PL230)");
-    if ( ID_Check(&pl230_udma_id[0],    CMSDK_PL230_BASE    ) == 1 ) err_code |= 1<<15;
+  //puts ("15: DMAC 0 (PL230)");
+  //  if ( ID_Check(&pl230_udma_id[0],    CMSDK_PL230_BASE    ) == 1 ) err_code |= 1<<15;
 
 
   /* Report error code */