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  • dev
  • feat_accel_decouple
  • feat_accel_hash_stream
  • feat_dma230_dataio
  • feat_dma350
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  • feat_extio
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  • nanosoc-2023
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  • soclabs/nanosoc_tech
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  • dev
  • feat_accel_decouple
  • feat_accel_hash_stream
  • feat_dma230_dataio
  • feat_dma350
  • feat_dmax4
  • feat_extio
  • feat_nanosoc_regions
  • feat_qspi_rom
  • main
  • nanosoc-2023
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...@@ -18,6 +18,9 @@ ...@@ -18,6 +18,9 @@
// ============= NanoSoC IP search path ============= // ============= NanoSoC IP search path =============
// NanoSoC Chip Pads Level // NanoSoC Chip Pads Level
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_pads.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_axis_initiator.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_ifsm.v
$(SOCLABS_NANOSOC_TECH_DIR)/extio8x4-axis/rtl/extio8x4_sync.v
// Include NanoSoC IP // Include NanoSoC IP
-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist -f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_ip.flist
...@@ -29,4 +32,4 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_ ...@@ -29,4 +32,4 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_chip/pads/glib/verilog/nanosoc_chip_
-f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_qs.flist -f $(SOCLABS_SLCOREM0_TECH_DIR)/flist/slcorem0_qs.flist
// Debug IP // Debug IP
-f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist -f $(SOCLABS_SOCDEBUG_TECH_DIR)/flist/socdebug.flist
\ No newline at end of file