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  • soclabs/nanosoc_tech
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.gitmodules
View file @ 55eaa51a
......@@ -10,3 +10,6 @@
[submodule "nanosoc/sldma350_tech"]
path = nanosoc/sldma350_tech
url = https://git.soton.ac.uk/soclabs/sldma350_tech.git
[submodule "nanosoc/sl_ams_tech"]
path = nanosoc/sl_ams_tech
url = https://git.soton.ac.uk/soclabs/sl_ams_tech.git
flist/nanosoc_ip.flist
View file @ 55eaa51a
......@@ -52,6 +52,7 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/expram_l/verilog/nanosoc_reg
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_apb_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
// NanoSoC Regions - SysTable Region
......@@ -63,4 +64,3 @@ $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_clkctrl.v
$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/nanosoc_control/verilog/nanosoc_pin_mux.v
flows/makefile.asic
View file @ 55eaa51a
......@@ -62,16 +62,16 @@ RTL_SOCKET_DIR := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_packages
flist_dc_nanosoc: gen_defs
@mkdir -p $(TCL_ASIC_FLIST_DIR)
@(cd $(TCL_ASIC_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(DC_OUTPUT_FILELIST) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -s -a -f $(DESIGN_VC) -o $(DC_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_ASIC_DIR)/src;)
flist_genus_nanosoc: gen_defs
@mkdir -p $(TCL_ASIC_FLIST_DIR)
@(cd $(TCL_ASIC_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -g -f $(DESIGN_VC) -o $(GENUS_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/synthesis/src -d $(NANOSOC_DEFINES);)
flist_formality_nanosoc: gen_defs
@(cd $(TCL_ASIC_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -F -a -f $(DESIGN_VC) -o $(FORMALITY_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/synthesis/src;)
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -F -a -f $(DESIGN_VC) -o $(FORMALITY_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/synthesis/src;)
gen_memories: bootrom
@mkdir -p $(MEMORIES_DIR)
......
flows/makefile.fpga
View file @ 55eaa51a
......@@ -68,7 +68,7 @@ code:
flist_tcl_nanosoc: gen_defs
@mkdir -p $(TCL_FLIST_DIR)
@(cd $(TCL_FLIST_DIR); \
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -i $(FLIST_INCLUDES) -r $(IMP_NANOSOC_DIR)/src -d $(NANOSOC_DEFINES);)
# Package NanoSoC Socket Components
package_socket:
......
flows/makefile.simulate
View file @ 55eaa51a
......@@ -22,10 +22,14 @@ MTI_VC_OPTIONS += -f $(TBENCH_VC) $(ADP_OPTIONS)
MTI_RUN_OPTIONS = -voptargs=+acc
# VCS options
VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug
VCS_OPTIONS = +vcs+lic+wait +v2k -sverilog -override_timescale=1ns/1ps +lint=all,noTMR,noVCDE -debug -debug_access+all
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
ifdef AMS
VCS_OPTIONS += -ad=$(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/vcsAD.init -ams_discipline logic -ams
endif
# XM verilog options
XMSIM_OPTIONS = -unbuffered -64bit -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = -f $(TBENCH_VC) $(ADP_OPTIONS)
......@@ -82,7 +86,7 @@ flist_vfiles_nanosoc: gen_defs
@if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir -p $(SIM_DIR)/logs; \
fi
@cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -v -o tbench.vc
@cd $(SIM_DIR); python $(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -f $(TBENCH_VC) -a -i $(FLIST_INCLUDES) -v -o tbench.vc
# ------- VCS -----------
......
makefile
View file @ 55eaa51a
......@@ -9,6 +9,7 @@
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
include $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc.config
#-------------------------------------
# - Commonly Overloaded Variables
......@@ -25,8 +26,10 @@ ACCELERATOR ?= yes
# Is the Arm QuickStart being used?
QUICKSTART ?= no
# IS this for an ASIC Flow?
ASIC ?= no
# Are simulations to be run in fast mode? (i.e. RAMs preloaded)
FAST_SIM ?= yes
#-------------------------------------
......@@ -67,11 +70,62 @@ ifeq ($(ACCELERATOR),yes)
NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
endif
# Set variables for tesbench if fast simulation
ifeq ($(FAST_SIM),yes)
DEFINES_VC += +define+FAST_SIM
NANOSOC_DEFINES += FAST_SIM
endif
ifdef DMA_DMA350_INCLUDE
ifdef DMA350_SMALL
NANOSOC_DEFINES += DMAC_DMA350
FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb_small.flist
endif
ifdef DMA350_DEFAULT
NANOSOC_DEFINES += DMAC_DMA350 DMA350_STREAM_2
FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
endif
ifdef DMA350_BIG
NANOSOC_DEFINES += DMAC_DMA350 DMA350_STREAM_2 DMA350_STREAM_3
FLIST_INCLUDES += $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb_big.flist
endif
else
ifdef DMA_0_PL230_INCLUDE
NANOSOC_DEFINES += DMAC_0_PL230
FLIST_INCLUDES +=$(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
endif
ifdef DMA_1_PL230_INCLUDE
NANOSOC_DEFINES += DMAC_1_PL230
FLIST_INCLUDES +=$(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
endif
endif
ifdef ADC_0_INCLUDE
AMS = yes
NANOSOC_DEFINES += AMS_PERIPHERALS ADC_0_INCLUDE
FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
endif
ifdef ADC_1_INCLUDE
AMS = yes
NANOSOC_DEFINES += AMS_PERIPHERALS ADC_1_INCLUDE
FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
endif
ifdef ADC_2_INCLUDE
AMS = yes
NANOSOC_DEFINES += AMS_PERIPHERALS ADC_2_INCLUDE
FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
endif
ifdef ADC_3_INCLUDE
AMS = yes
NANOSOC_DEFINES += AMS_PERIPHERALS ADC_3_INCLUDE
FLIST_INCLUDES += $(SOCLABS_NANOSOC_TECH_DIR)/nanosoc/sl_ams_tech/SL_ADC_8bits/flist/sl_adc_8bits_ip.flist
endif
# System Design Filelist
ifeq ($(QUICKSTART),yes)
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_qs.flist
......@@ -84,21 +138,19 @@ else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top_ASIC.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
NANOSOC_DEFINES += DMAC_0_PL230 DMAC_1_PL230 ASIC_TEST_PORTS POWER_PINS
NANOSOC_DEFINES += ASIC_TEST_PORTS POWER_PINS
else
DESIGN_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
TBENCH_VC ?= $(SOCLABS_PROJECT_DIR)/flist/project/top.flist
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
TB_TOP ?= nanosoc_tb
NANOSOC_DEFINES += DMAC_0_PL230
endif
endif
# Make variables visible to target shells
export ARM_CORTEX_M0_DIR
export ARM_CORSTONE_101_DIR
export FLIST_INCLUDES
export AMS
# Location of Defines File
DEFINES_DIR := $(SOCLABS_PROJECT_DIR)/system/src/defines/
DEFINES_FILE := $(DEFINES_DIR)/gen_defines.v
......@@ -132,6 +184,9 @@ gen_defs:
@mkdir -p $(DEFINES_DIR)
@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
TEST_AMS:
$(info AMS is $(AMS))
$(info VCS OPTIONS is $(VCS_OPTIONS))
# Remove RTL compile files, log files, software compile files
clean : clean_all_code
@rm -rf $(SIM_TOP_DIR)
nanosoc.config 0 → 100644
View file @ 55eaa51a
#-----------------------------------------------------------------------------
# NanoSoC Configuration file
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#### IP Configuration
# !!EDIT this to point to the relevant logical directories of IP
ARM_CORSTONE_101_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Corstone-101/logical
ARM_CORTEX_M0_DIR ?= $(ARM_IP_LIBRARY_PATH)/latest/Cortex-M0/logical
# DMA_xxx_INCLUDE (yes or leave blank)
DMA_0_PL230_INCLUDE := yes
DMA_1_PL230_INCLUDE :=
DMA_DMA350_INCLUDE :=
# DMA 350 options set to yes for one of them
# !! MAKE sure you run the correct configuration in the SLDMA350 directory
# Small configuration of DMA, 2 channels, no stream interface, no extended features
# Default configuration of DMA, 2 channels, stream interface, extended features
# Big configuration of DMA, 3 channels, stream interface, extended features
DMA350_SMALL :=
DMA350_DEFAULT :=
DMA350_BIG :=
# ADC Include (yes or leave blank)
ADC_0_INCLUDE:=
ADC_1_INCLUDE:=
ADC_2_INCLUDE:=
ADC_3_INCLUDE:=
\ No newline at end of file
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_region_sysio.v
View file @ 55eaa51a
......@@ -10,6 +10,7 @@
//
// Copyright 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
`include "gen_defines.v"
module nanosoc_region_sysio #(
parameter SYS_ADDR_W=32, // System Address Width
......@@ -108,7 +109,8 @@ module nanosoc_region_sysio #(
localparam BASEADDR_APBSS = 32'h4000_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO0 = 32'h4001_0000; // GPIO0 peripheral base address
localparam BASEADDR_GPIO1 = 32'h4001_1000; // GPIO1 peripheral base address
localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral basse address
localparam BASEADDR_SYSCTRL = 32'h4001_f000; // Sysctrl peripheral base address
localparam BASEADDR_ADC = 32'h4002_0000; // ADC Peripheral base address
localparam BE = 0;
// ------------------------------------------------------------
......@@ -140,13 +142,20 @@ module nanosoc_region_sysio #(
wire [SYS_DATA_W-1:0] sysctrl_hrdata;
wire sysctrl_hresp;
wire adcsys_hsel; // ADC subsystem AHB interface signals
wire adcsys_hreadyout;
wire [SYS_DATA_W-1:0] adcsys_hrdata;
wire adcsys_hresp;
// AHB address decode
nanosoc_sysio_decode #(
.BASEADDR_APBSS (BASEADDR_APBSS),
.BASEADDR_GPIO0 (BASEADDR_GPIO0),
.BASEADDR_GPIO1 (BASEADDR_GPIO1),
.BASEADDR_SYSCTRL (BASEADDR_SYSCTRL)
.BASEADDR_SYSCTRL (BASEADDR_SYSCTRL),
.BASEADDR_ADC (BASEADDR_ADC)
) u_addr_decode (
// System Address
.hsel (HSEL),
......@@ -155,9 +164,16 @@ module nanosoc_region_sysio #(
.gpio0_hsel (gpio0_hsel),
.gpio1_hsel (gpio1_hsel),
.sysctrl_hsel (sysctrl_hsel),
`ifdef AMS_PERIPHERALS
.adcsys_hsel (adcsys_hsel),
`endif
.defslv_hsel (defslv_hsel)
);
`ifdef AMS_PERIPHERALS
parameter AMS_PERIPHERAL_PORT = 1;
`else
parameter AMS_PERIPHERAL_PORT = 0;
`endif
// AHB slave multiplexer
cmsdk_ahb_slave_mux #(
.PORT0_ENABLE (1), // APB subsystem bridge
......@@ -165,7 +181,7 @@ module nanosoc_region_sysio #(
.PORT2_ENABLE (1), // GPIO Port 1
.PORT3_ENABLE (1), // SYS control
.PORT4_ENABLE (1), // Default
.PORT5_ENABLE (0),
.PORT5_ENABLE (AMS_PERIPHERAL_PORT), // ADC Region
.PORT6_ENABLE (0),
.PORT7_ENABLE (0),
.PORT8_ENABLE (0),
......@@ -195,10 +211,10 @@ module nanosoc_region_sysio #(
.HREADYOUT4 (defslv_hreadyout),
.HRESP4 (defslv_hresp),
.HRDATA4 (defslv_hrdata),
.HSEL5 (1'b0), // Input Port 5
.HREADYOUT5 (defslv_hreadyout),
.HRESP5 (defslv_hresp),
.HRDATA5 (defslv_hrdata),
.HSEL5 (adcsys_hsel), // Input Port 5
.HREADYOUT5 (adcsys_hreadyout),
.HRESP5 (adcsys_hresp),
.HRDATA5 (adcsys_hrdata),
.HSEL6 (1'b0), // Input Port 6
.HREADYOUT6 (defslv_hreadyout),
.HRESP6 (defslv_hresp),
......@@ -429,4 +445,63 @@ module nanosoc_region_sysio #(
.watchdog_reset (WDOGRESETREQ)
);
`ifdef AMS_PERIPHERALS
nanosoc_sysio_adc_ss #(
`ifdef ADC_0_INCLUDE
.ADC_0_ENABLE (1),
`endif
`ifdef ADC_1_INCLUDE
.ADC_1_ENABLE (1),
`endif
`ifdef ADC_2_INCLUDE
.ADC_2_ENABLE (1),
`endif
`ifdef ADC_3_INCLUDE
.ADC_3_ENABLE (1),
`endif
.INCLUDE_IRQ_SYNCHRONIZER(0), // require IRQs to be HCLK synchronous
.INCLUDE_APB_TEST_SLAVE (1), // Include example test slave
.BE (BE)
) u_sysio_adc_ss (
`ifdef ADC_0_ENABLE
.adc_0_in(),
.i_adc_0_irq(),
`endif
`ifdef ADC_1_ENABLE
.adc_1_in(),
.i_adc_1_irq(),
`endif
`ifdef ADC_2_ENABLE
.adc_2_in(),
.i_adc_1_irq(),
`endif
`ifdef ADC_3_ENABLE
.adc_3_in(),
.i_adc_1_irq(),
`endif
.HCLK(HCLK),
.HRESETn(HRESETn),
.HSEL(adcsys_hsel),
.HADDR(HADDR[15:0]),
.HTRANS(HTRANS[1:0]),
.HWRITE(HWRITE),
.HSIZE(HSIZE),
.HPROT(HPROT),
.HREADY(HREADY),
.HWDATA(HWDATA[31:0]),
.HREADYOUT(adcsys_hreadyout),
.HRDATA(adcsys_hrdata),
.HRESP(adcsys_hresp),
.PCLK(PCLK), // Peripheral clock
.PCLKG(PCLKG), // Gate PCLK for bus interface only
.PCLKEN(PCLKEN), // Clock divider for AHB to APB bridge
.PRESETn(PRESETn) // APB reset
);
`endif
endmodule
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_adc_ss.v 0 → 100755
View file @ 55eaa51a
This diff is collapsed.
nanosoc/nanosoc_regions/sysio/verilog/nanosoc_sysio_decode.v
View file @ 55eaa51a
......@@ -37,6 +37,7 @@
// Also performs address decode for MTB
//-----------------------------------------------------------------------------
//
`include "gen_defines.v"
module nanosoc_sysio_decode #(
parameter SYS_ADDR_W = 32,
......@@ -47,8 +48,9 @@ module nanosoc_sysio_decode #(
// GPIO1 peripheral base address
parameter BASEADDR_GPIO1 = 32'h4001_1000,
// Sysctrl base address
parameter BASEADDR_SYSCTRL = 32'h4001_f000
)(
parameter BASEADDR_SYSCTRL = 32'h4001_f000,
parameter BASEADDR_ADC = 32'h4002_0000
)(
// System Address
input wire hsel,
input wire [SYS_ADDR_W-1:0] haddr,
......@@ -58,7 +60,9 @@ module nanosoc_sysio_decode #(
output wire gpio0_hsel,
output wire gpio1_hsel,
output wire sysctrl_hsel,
`ifdef AMS_PERIPHERALS
output wire adcsys_hsel,
`endif
// Default slave
output wire defslv_hsel
);
......@@ -81,14 +85,24 @@ module nanosoc_sysio_decode #(
BASEADDR_GPIO1[31:12]); // 0x40011000
assign sysctrl_hsel = hsel & (haddr[31:12]==
BASEADDR_SYSCTRL[31:12]); // 0x4001F000
`ifdef AMS_PERIPHERALS
assign adcsys_hsel = hsel & (haddr[31:12]==
BASEADDR_ADC[31:12]); // 0x40020000
`endif
// ----------------------------------------------------------
// Default slave decode logic
// ----------------------------------------------------------
`ifdef AMS_PERIPHERALS
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel | adcsys_hsel
);
`else
assign defslv_hsel = ~(apbsys_hsel |
gpio0_hsel | gpio1_hsel |
sysctrl_hsel
);
`endif
endmodule
sl_ams_tech @ a4a0fcf6
Subproject commit a4a0fcf677a5b5c0cdcd08062ad2e50f1129d5a0
software/common/validation/adc_tests.c 0 → 100644
View file @ 55eaa51a
/*
*-----------------------------------------------------------------------------
* The confidential and proprietary information contained in this file may
* only be used by a person authorised under and to the extent permitted
* by a subsisting licensing agreement from Arm Limited or its affiliates.
*
* (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
* ALL RIGHTS RESERVED
*
* This entire notice must be reproduced on all copies of this file
* and copies of this file may only be made by a person if such person is
* permitted to do so under the terms of a subsisting license agreement
* from Arm Limited or its affiliates.
*
* SVN Information
*
* Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
*
* Revision : $Revision: 371321 $
*
* Release Information : Cortex-M System Design Kit-r1p1-00rel0
*-----------------------------------------------------------------------------
*/
/*
A simple test to check the operation of APB slave multiplexer
*/
#ifdef CORTEX_M0
#include "CMSDK_CM0.h"
#endif
#ifdef CORTEX_M0PLUS
#include "CMSDK_CM0plus.h"
#endif
#ifdef CORTEX_M3
#include "CMSDK_CM3.h"
#endif
#ifdef CORTEX_M4
#include "CMSDK_CM4.h"
#endif
#include <stdio.h>
#include "uart_stdout.h"
#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
#define HW16_REG(ADDRESS) (*((volatile unsigned short *)(ADDRESS)))
#define HW8_REG(ADDRESS) (*((volatile unsigned char *)(ADDRESS)))
int adc_detect(void);
int adc_check_clk_div(void);
#if defined ( __CC_ARM )
__asm void address_test_write(unsigned int addr, unsigned int wdata);
__asm unsigned int address_test_read(unsigned int addr);
#else
void address_test_write(unsigned int addr, unsigned int wdata);
unsigned int address_test_read(unsigned int addr);
#endif
void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value);
int ID_Check(const unsigned int id_array[], unsigned int offset);
int APB_test_slave_Check(unsigned int offset);
/* Global variables */
volatile int hardfault_occurred;
volatile int hardfault_expected;
volatile int temp_data;
int hardfault_verbose=0; // 0:Not displaying anything in hardfault handler
#define SL_ADC_BASE (0x40020000UL)
#define SL_ADC_0_BASE (SL_ADC_BASE + 0x0000UL)
int main (void)
{
int err_code = 0;
int data[64];
int i;
// UART init
UartStdOutInit();
// Test banner message and revision number
puts("\nCortex Microcontroller System Design Kit");
puts(" - ADC test - revision $Revision: 371321 $\n");
if(adc_detect()!=0) {
return 0; // Quit test if ADC not present
}
err_code += adc_check_clk_div();
address_test_write(SL_ADC_0_BASE + 0x00C, 0x01);
printf("Enable ADC... \n");
printf("Read ADC Data: \n");
for (i =0; i<64; i++){
while(!address_test_read(SL_ADC_0_BASE+0x004)){;}
data[i]=address_test_read(SL_ADC_0_BASE);
}
for (i =0; i<64; i++){
printf("0x%02x \n",data[i]);
}
if (err_code==0) {
printf ("\n** TEST PASSED **\n");
} else {
printf ("\n** TEST FAILED **, Error code = (0x%x)\n", err_code);
}
UartEndSimulation();
return 0;
}
int adc_check_clk_div(void)
{
int clk_div_actual;
puts("Testing Clock Divider read/write access \n");
clk_div_actual = address_test_read(SL_ADC_0_BASE + 0x008);
printf("Clock divider after reset: %d\n", clk_div_actual);
address_test_write(SL_ADC_0_BASE + 0x008, 0x5E);
printf("Clock divider set to: 0x5E\n");
clk_div_actual = address_test_read(SL_ADC_0_BASE + 0x008);
printf("Clock divider set read: 0x%02X\n", clk_div_actual);
if(clk_div_actual!=0x320)
{
return 1;
}
else{
return 0;
}
}
int adc_detect(void)
{
int result;
int volatile rdata;
unsigned const int adc_id[16] = {0x53, 0x4C, 0x00, 0x61, 0x64, 0x63, 0x00, 0x08};
puts("Detect if ADC is present...");
hardfault_occurred = 0;
hardfault_expected = 1;
rdata = address_test_read(SL_ADC_0_BASE+ 0xFE0);
hardfault_expected = 0;
result = hardfault_occurred ? 1 : ID_Check(&adc_id[0], SL_ADC_0_BASE);
hardfault_occurred = 0;
if (result!=0) {
puts("** TEST SKIPPED ** ADC is not present.\n");
UartEndSimulation();
}
return(result);
}
int ID_Check(const unsigned int id_array[], unsigned int offset)
{
int i;
unsigned long expected_val, actual_val;
unsigned long compare_mask;
int mismatch = 0;
unsigned long test_addr;
/* Check the peripheral ID and component ID */
for (i=0;i<8;i++) {
test_addr = offset + 4*i + 0xFC0;
expected_val = id_array[i];
actual_val = HW32_REG(test_addr);
/* create mask to ignore version numbers */
if (i==2) { compare_mask = 0xF0;} // mask out version field
else { compare_mask = 0x00;} // compare whole value
if ((expected_val & (~compare_mask)) != (actual_val & (~compare_mask))) {
printf ("Difference found: %x, expected %x, actual %x\n", test_addr, expected_val, actual_val);
mismatch++;
}
} // end_for
return (mismatch);
}
#if defined ( __CC_ARM )
/* Test function for write - for ARM / Keil */
__asm void address_test_write(unsigned int addr, unsigned int wdata)
{
STR R1,[R0]
DSB ; Ensure bus fault occurred before leaving this subroutine
BX LR
}
#else
/* Test function for write - for gcc */
void address_test_write(unsigned int addr, unsigned int wdata) __attribute__((naked));
void address_test_write(unsigned int addr, unsigned int wdata)
{
__asm(" str r1,[r0]\n"
" dsb \n"
" bx lr \n"
);
}
#endif
/* Test function for read */
#if defined ( __CC_ARM )
/* Test function for read - for ARM / Keil */
__asm unsigned int address_test_read(unsigned int addr)
{
LDR R1,[R0]
DSB ; Ensure bus fault occurred before leaving this subroutine
MOVS R0, R1
BX LR
}
#else
/* Test function for read - for gcc */
unsigned int address_test_read(unsigned int addr) __attribute__((naked));
unsigned int address_test_read(unsigned int addr)
{
__asm(" ldr r1,[r0]\n"
" dsb \n"
" movs r0, r1 \n"
" bx lr \n"
);
}
#endif
#if defined ( __CC_ARM )
/* ARM or Keil toolchain */
__asm void HardFault_Handler(void)
{
MOVS r0, #4
MOV r1, LR
TST r0, r1
BEQ stacking_used_MSP
MRS R0, PSP ; // first parameter - stacking was using PSP
B get_LR_and_branch
stacking_used_MSP
MRS R0, MSP ; // first parameter - stacking was using MSP
get_LR_and_branch
MOV R1, LR ; // second parameter is LR current value
LDR R2,=__cpp(HardFault_Handler_c)
BX R2
ALIGN
}
#else
/* gcc toolchain */
void HardFault_Handler(void) __attribute__((naked));
void HardFault_Handler(void)
{
__asm(" movs r0,#4\n"
" mov r1,lr\n"
" tst r0,r1\n"
" beq stacking_used_MSP\n"
" mrs r0,psp\n" /* first parameter - stacking was using PSP */
" ldr r1,=HardFault_Handler_c \n"
" bx r1\n"
"stacking_used_MSP:\n"
" mrs r0,msp\n" /* first parameter - stacking was using PSP */
" ldr r1,=HardFault_Handler_c \n"
" bx r1\n"
".pool\n" );
}
#endif
/* C part of the fault handler - common between ARM / Keil /gcc */
void HardFault_Handler_c(unsigned int * hardfault_args, unsigned lr_value)
{
unsigned int stacked_pc;
unsigned int stacked_r0;
hardfault_occurred++;
if (hardfault_verbose) puts ("[Hard Fault Handler]");
if (hardfault_expected==0) {
puts ("ERROR : Unexpected HardFault interrupt occurred.\n");
UartEndSimulation();
while (1);
}
stacked_r0 = ((unsigned long) hardfault_args[0]);
stacked_pc = ((unsigned long) hardfault_args[6]);
if (hardfault_verbose) printf(" - Stacked R0 : 0x%x\n", stacked_r0);
if (hardfault_verbose) printf(" - Stacked PC : 0x%x\n", stacked_pc);
/* Modify R0 to a valid address */
hardfault_args[0] = (unsigned long) &temp_data;
return;
}
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testcodes/adc_tests/makefile 0 → 100644
View file @ 55eaa51a
#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#
# SVN Information
#
# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
#
# Revision : $Revision: 371321 $
#
# Release Information : Cortex-M System Design Kit-r1p1-00rel0
#-----------------------------------------------------------------------------
#
# Cortex-M System Design Kit software compilation make file
#
#-----------------------------------------------------------------------------
#
# Configurations
#
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0PLUS
TARGET = arm-none-eabi
# Shared software directory
SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
else
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
endif
# Program file
TESTNAME = adc_tests
# Endian Option
COMPILE_BIGEND = 0
# Configuration
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
USER_DEFINE = -DCORTEX_M0PLUS
else
USER_DEFINE = -DCORTEX_M0
endif
DEPS_LIST = makefile
# Tool chain : ds5 / gcc / keil
TOOL_CHAIN = ds5
ifeq ($(TOOL_CHAIN),ds5)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = --cpu Cortex-M0plus
else
CPU_TYPE = --cpu Cortex-M0
endif
endif
ifeq ($(TOOL_CHAIN),ds6)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = -mcpu=Cortex-M0plus
else
CPU_TYPE = -mcpu=Cortex-M0
endif
endif
ifeq ($(TOOL_CHAIN),gcc)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = -mcpu=cortex-m0plus
else
CPU_TYPE = -mcpu=cortex-m0
endif
endif
# Startup code directory for DS-5
ifeq ($(TOOL_CHAIN),ds5)
STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
endif
ifeq ($(TOOL_CHAIN),ds6)
STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
endif
# Startup code directory for gcc
ifeq ($(TOOL_CHAIN),gcc)
STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
STARTUP_FILE = startup_CMSDK_CM0plus
SYSTEM_FILE = system_CMSDK_CM0plus
else
STARTUP_FILE = startup_CMSDK_CM0
SYSTEM_FILE = system_CMSDK_CM0
endif
# ---------------------------------------------------------------------------------------
# D5-5 options
# MicroLIB option
COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
ifeq ($(TOOL_CHAIN),ds6)
ARM_TARGET = --target=arm-$(TARGET)
CC_TOOL = armclang -O1
ASM_TOOL = armclang -masm=armasm $(ARM_TARGET) -c
else
CC_TOOL = armcc -O3
ASM_TOOL = armasm
ARM_TARGET = -Otime
endif
ARM_CC_OPTIONS = $(ARM_TARGET) -c -g -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
ARM_ASM_OPTIONS = -g
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--rw_base 0x30000000 --ro_base 0x00000000 --map
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
ARM_CC_OPTIONS += --bigend
ARM_ASM_OPTIONS += --bigend
ARM_LINK_OPTIONS += --be8
endif
ifeq ($(COMPILE_MICROLIB),1)
# MicroLIB
ARM_CC_OPTIONS += --library_type=microlib
ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
ARM_LINK_OPTIONS += --library_type=microlib
endif
ifeq ($(COMPILE_SMALLMUL),1)
# In Cortex-M0, small multiply takes 32 cycles
ARM_CC_OPTIONS += --multiply_latency=32
endif
# ---------------------------------------------------------------------------------------
# gcc options
GNG_CC = $(TARGET)-gcc
GNU_OBJDUMP = $(TARGET)-objdump
GNU_OBJCOPY = $(TARGET)-objcopy
LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
GNU_CC_FLAGS += -mbig-endian
endif
# ---------------------------------------------------------------------------------------
all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# DS-5
all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
all_ds6 : $(TESTNAME).hex $(TESTNAME).lst
$(TESTNAME).o : $(SOFTWARE_DIR)/common/validation/$(TESTNAME).c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
$(CC_TOOL) $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
$(ASM_TOOL) $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
$(TESTNAME).ELF : $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
$(TESTNAME).hex : $(TESTNAME).ELF
fromelf --vhx --8x1 $< --output $@
$(TESTNAME).lst : $(TESTNAME).ELF makefile
fromelf -c -d -e -s $< --output $@
# ---------------------------------------------------------------------------------------
# gcc
all_gcc:
$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
$(SOFTWARE_DIR)/common/validation/$(TESTNAME).c \
$(SOFTWARE_DIR)/common/retarget/retarget.c \
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \
$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
# Generate disassembly code
$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
# Generate binary file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
# Generate hex file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
# Note:
# If the version of object copy you are using does not support verilog hex file output,
# you can generate the hex file from binary file using the following command
# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Keil MDK
all_keil:
@echo "Please compile your project code and press ENTER when ready"
@read dummy
# ---------------------------------------------------------------------------------------
# Binary
all_bin: $(TESTNAME).bin
# Generate hex file from binary
od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Clean
clean :
@rm -rf *.o
@if [ -e $(TESTNAME).hex ] ; then \
rm -rf $(TESTNAME).hex ; \
fi
@if [ -e $(TESTNAME).lst ] ; then \
rm -rf $(TESTNAME).lst ; \
fi
@if [ -e $(TESTNAME).ELF ] ; then \
rm -rf $(TESTNAME).ELF ; \
fi
@if [ -e $(TESTNAME).bin ] ; then \
rm -rf $(TESTNAME).bin ; \
fi
@rm -rf *.crf
@rm -rf *.plg
@rm -rf *.tra
@rm -rf *.htm
@rm -rf *.map
@rm -rf *.dep
@rm -rf *.d
@rm -rf *.lnp
@rm -rf *.bak
@rm -rf *.lst
@rm -rf *.axf
@rm -rf *.sct
@rm -rf *.__i
@rm -rf *._ia
verif/tb/verilog/nanosoc_tb_qs.v
View file @ 55eaa51a
......@@ -289,9 +289,16 @@ reg baud_clk_del;
wire rxd8_tvalid;
wire [7:0] rxd8_tdata ;
`ifdef FAST_SIM
parameter FAST_LOAD = 1;
`else
parameter FAST_LOAD = 0;
`endif
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME)
.TXDFILENAME(ADP_FILENAME),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_8_txd_from_file (
.aclk (CLK),
.aresetn (NRST),
......