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.gitlab-ci.yml
View file @ f68c3e62
......@@ -33,18 +33,8 @@ simulate-nanosoc:
build-job-Z2: # This job runs in the build stage, which runs first.
stage: build
script:
# setup vivado environment for Vivado 2021.1
- source /tools/Xilinx/Vivado/2021.1/.settings64-Vivado.sh
# move and unpack the arm ip into the arm-AAA-ip folder, below the working directory
- cp -r /home/gitlab-runner/arm-AAA-ip ../arm-AAA-ip
- cd ../arm-AAA-ip/Corstone-101_Foundation_IP/
- tar -xf BP210-r1p1-00rel0.tar.gz
- cd ../Cortex-M0/
- tar -xf AT510-r0p0-03rel2.tar.gz
- cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc_tech/system/fpga_imp/
- cd ./system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds6
......@@ -56,9 +46,6 @@ build-job-Z2: # This job runs in the build stage, which runs first.
- echo "Build failed"
- exit 1
- fi
# cleanup arm-AAA-ip directory
- cd ../../../
- rm -r arm-AAA-ip
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
......@@ -71,16 +58,8 @@ build-job-Z2: # This job runs in the build stage, which runs first.
build-job-ZCU104: # This job runs in the build stage, which runs first.
stage: build
script:
# move and unpack the arm ip into the arm-AAA-ip folder, below the working directory
- cp -r /home/dwn1c21/arm-AAA-ip ../arm-AAA-ip
- cd ../arm-AAA-ip/Corstone-101_Foundation_IP/
- tar -xf BP210-r1p1-00rel0.tar.gz
- cd ../Cortex-M0/
- tar -xf AT510-r0p0-03rel2.tar.gz
- cd ../DMA-230_MicroDMA_Controller/
- tar -xf PL230-r0p0-02rel2-1.tar.gz
# move to fpga_imp directory and run the fpga build script for pynq z2
- cd ../../nanosoc_tech/system/fpga_imp/
- cd ./system/fpga_imp/
- source ../../set_env.sh
- mkdir -p $NANOSOC_TECH_DIR/system/src/bootrom
- make -C $NANOSOC_TECH_DIR/system bootrom SIM_TOP_DIR=$NANOSOC_TECH_DIR/sim BOOTROM_BUILD_DIR=$NANOSOC_TECH_DIR/system/src/bootrom TOOL_CHAIN=ds5
......@@ -92,9 +71,6 @@ build-job-ZCU104: # This job runs in the build stage, which runs first.
- echo "Build failed"
- exit 1
- fi
# cleanup arm-AAA-ip directory
- cd ../../../
- rm -r arm-AAA-ip
artifacts:
paths:
# Keep the generated bit and hwh file from fpga build script
......
system/aes/src/nanosoc_acc_wrapper.v 0 → 100644
View file @ f68c3e62
//-----------------------------------------------------------------------------
// SoC Labs Basic Example Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_acc_wrapper #(
parameter AHBADDRWIDTH=16,
parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=128,
parameter CFGNUMIRQ=4
) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSELS,
input wire [AHBADDRWIDTH-1:0] HADDRS,
input wire [1:0] HTRANSS,
input wire [2:0] HSIZES,
input wire [3:0] HPROTS,
input wire HWRITES,
input wire HREADYS,
input wire [31:0] HWDATAS,
output wire HREADYOUTS,
output wire HRESPS,
output wire [31:0] HRDATAS,
// Input Data Request Signal to DMAC
output wire exp_drq_ip_o,
input wire exp_dlast_ip_i,
// Output Data Request Signal to DMAC
output wire exp_drq_op_o,
input wire exp_dlast_op_i,
// Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o
);
soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSELS),
.ahb_haddr16 (HADDRS[15:0]),
.ahb_htrans (HTRANSS),
.ahb_hwrite (HWRITES),
.ahb_hsize (HSIZES),
.ahb_hprot (HPROTS),
.ahb_hwdata (HWDATAS),
.ahb_hready (HREADYS),
.ahb_hrdata (HRDATAS),
.ahb_hreadyout (HREADYOUTS),
.ahb_hresp (HRESPS),
.drq_ipdma128 (exp_drq_ip_o),
.dlast_ipdma128 (1'b0),
.drq_opdma128 (exp_drq_op_o),
.dlast_opdma128 (1'b0),
.irq_key128 (exp_irq_o[0]),
.irq_ip128 (exp_irq_o[1]),
.irq_op128 (exp_irq_o[2]),
.irq_error (exp_irq_o[3]),
.irq_merged ( )
);
endmodule
system/aes/src/nanosoc_exp_wrapper.v 0 → 100644
View file @ f68c3e62
//-----------------------------------------------------------------------------
// SoC Labs Basic Example Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_exp_wrapper #(
parameter AHBADDRWIDTH=16,
parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=128,
parameter CFGNUMIRQ=4
) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSEL_i,
input wire [AHBADDRWIDTH-1:0] HADDR_i,
input wire [1:0] HTRANS_i,
input wire [2:0] HSIZE_i,
input wire [3:0] HPROT_i,
input wire HWRITE_i,
input wire HREADY_i,
input wire [31:0] HWDATA_i,
output wire HREADYOUT_o,
output wire HRESP_o,
output wire [31:0] HRDATA_o,
// Input Data Request Signal to DMAC
output wire exp_drq_ip_o,
input wire exp_dlast_ip_i,
// Output Data Request Signal to DMAC
output wire exp_drq_op_o,
input wire exp_dlast_op_i,
// Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o
);
soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSEL_i),
.ahb_haddr16 (HADDR_i[15:0]),
.ahb_htrans (HTRANS_i),
.ahb_hwrite (HWRITE_i),
.ahb_hsize (HSIZE_i),
.ahb_hprot (HPROT_i),
.ahb_hwdata (HWDATA_i),
.ahb_hready (HREADY_i),
.ahb_hrdata (HRDATA_o),
.ahb_hreadyout (HREADYOUT_o),
.ahb_hresp (HRESP_o),
.drq_ipdma128 (exp_drq_ip_o),
.dlast_ipdma128 (1'b0),
.drq_opdma128 (exp_drq_op_o),
.dlast_opdma128 (1'b0),
.irq_key128 (exp_irq_o[0]),
.irq_ip128 (exp_irq_o[1]),
.irq_op128 (exp_irq_o[2]),
.irq_error (exp_irq_o[3]),
.irq_merged ( )
);
endmodule
system/aes/src/soclabs_ahb_aes128_ctrl.v
View file @ f68c3e62
This diff is collapsed.
system/fpga_imp/scripts/build_mcu_fpga_ip.tcl
View file @ f68c3e62
......@@ -84,11 +84,14 @@ read_verilog $soc_vlog/verilog/nanosoc_mcu_sysctrl.v
read_verilog $soc_vlog/verilog/nanosoc_cpu.v
read_verilog $soc_vlog/verilog/nanosoc_sys_ahb_decode.v
read_verilog $soc_vlog/verilog/nanosoc_sysio.v
read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
read_verilog ../aes/src/nanosoc_acc_wrapper.v
read_verilog $soc_vlog/verilog/nanosoc_chip.v
read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
set search_path [ concat $search_path ../../../secworks-aes/src/rtl ]
read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
#set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
set_property top nanosoc_chip [current_fileset]
# FPGA specific timing constraints
......
system/makefile
View file @ f68c3e62
......@@ -6,7 +6,7 @@
#
# David Flynn (d.w.flynn@soton.ac.uk)
#
# Copyright � 2021-3, SoC Labs (www.soclabs.org)
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------
#-----------------------------------------------------------------------------
......@@ -81,21 +81,21 @@ BOOTROM_HEX ?= $(NANOSOC_TECH_DIR)/system/testcodes/bootloader/$(BOOTLOADE
BOOTROM_BUILD_DIR ?= $(NANOSOC_TECH_DIR)/system/src/bootrom
NANSOC_EXPANSION_REGION ?= yes
NANOSOC_EXPANSION_REGION ?= yes
# Simulator Defines
DEFINES_VC += $(MEM_INIT) +define+CORTEX_M0 +define+USE_TARMAC
ifeq ($(NANSOC_EXPANSION_REGION),yes)
DEFINES_VC += +define+NANSOC_EXPANSION_REGION
ifeq ($(NANOSOC_EXPANSION_REGION),yes)
DEFINES_VC += +define+NANOSOC_EXPANSION_REGION
endif
# Simulator Command file to specify RTL source files
TBENCH_VC ?= -f $(PROJECT_DIR)/flist/project/system.flist
TBENCH_VC ?= $(PROJECT_DIR)/flist/project/system.flist
# Simulator type (mti/vcs/xm)
SIMULATOR = xm
SIMULATOR = mti
# Directory to put simulation files
SIM_TOP_DIR ?= $(PROJECT_DIR)/simulate/sim
......@@ -105,16 +105,16 @@ SIM_DIR = $(SIM_TOP_DIR)/$(TESTNAME)
# MTI option
#DF#MTI_OPTIONS = -novopt
MTI_OPTIONS = -suppress 2892
MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
MTI_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# VCS option
VCS_OPTIONS = +vcs+lic+wait +v2k +lint=all,noTMR,noVCDE -debug
VCS_SIM_OPTION = +vcs+lic+wait +vcs+flush+log -assert nopostproc
VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC)
VCS_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# XM verilog option
XMSIM_OPTIONS = -unbuffered -status -LICQUEUE -f xmsim.args -cdslib cds.lib -hdlvar hdl.var -NBASYNC
XM_VC_OPTIONS = $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
XM_VC_OPTIONS = -f $(TBENCH_VC) $(ACCELERATOR_VC) $(ADP_OPTIONS)
# Debug Tester image
......@@ -142,7 +142,7 @@ all : all_$(SIMULATOR)
# Compile RTL
compile_vcs :
vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) | tee compile_vcs.log
vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) $(DEFINES_VC) | tee compile_vcs.log
# Run simulation in batch mode
......@@ -227,31 +227,37 @@ all_xm : compile_xm bootrom debugtester
# ------- MTI -----------
# Compile RTL
compile_mti :
compile_mti : bootrom
@echo ADP_FILE
@echo $(ADP_OPTIONS)
cd $(SIM_DIR)
@if [ -d work ] ; then \
true ; \
else \
vlib work; \
fi
vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) | tee compile_mti.log
cd $(SIM_DIR); vlog -incr -lint +v2k $(MTI_OPTIONS) $(MTI_VC_OPTIONS) $(DEFINES_VC) | tee compile_mti.log
# Run simulation in batch mode
run_mti : code
@if [ ! -d logs ] ; then \
mkdir logs; \
run_mti : code compile_mti
@if [ ! -d $(SIM_DIR)/logs ] ; then \
mkdir $(SIM_DIR)/logs; \
fi
vsim $(MTI_OPTIONS) -c tb_cmsdk_mcu -do "radix hex;run -all;quit -f" | tee logs/run_$(TESTNAME).log ;
@echo "run -all" > $(SIM_DIR)/run.tcl.tmp
@echo "quit -f" >> $(SIM_DIR)/run.tcl.tmp
@mv $(SIM_DIR)/run.tcl.tmp $(SIM_DIR)/run.tcl
cd $(SIM_DIR); vsim $(MTI_OPTIONS) -c nanosoc_tb -do run.tcl | tee logs/run_$(TESTNAME).log ;
# Run simulation in interactive mode
sim_mti : code
vsim $(MTI_OPTIONS) -gui tb_cmsdk_mcu &
sim_mti : code compile_mti
vsim $(MTI_OPTIONS) -gui nanosoc_tb &
# Create work directory
lib_mti :
vlib work
# Compile RTL, and run all tests in batch mode
all_mti : compile_mti bootrom debugtester
all_mti : bootrom compile_mti debugtester
@if [ ! -d logs ] ; then \
mkdir logs; \
fi
......@@ -320,6 +326,7 @@ endif
if [ -e $(TESTNAME).hex ] ; then \
mkdir -p $(SIM_DIR) ; \
cp $(TESTNAME).hex $(SIM_DIR)/image.hex ; \
cp $(TESTNAME).hex ../../image.hex ; \
else \
echo Problem reading hex file ;\
exit 1; \
......@@ -427,7 +434,7 @@ v2html:
fi
@(cd $(NANOSOC_HTML_DIR)/build; \
rm *.html; rm *.gif; rm *.gz; \
~/tools/v2html -f $(VERILOG_DIR)/v2html_M0.vc -ht nanosoc_chip ; \
~/tools/v2html -f $(PROJECT_DIR)/flist/project/v2html_system.flist -ht nanosoc_chip ; \
cp -p nanosoc_tb.v.html hierarchy.html ; \
cd $(SIM_DIR) ; )
gtar zcvf $(NANOSOC_HTML_DIR)/v2html_doc.tgz $(NANOSOC_HTML_DIR)/build
......
system/src/verilog/nanosoc_chip.v
View file @ f68c3e62
......@@ -833,17 +833,24 @@ localparam CORTEX_M0 = 1;
//
// ************************************************
wire exp_ip_req;
wire exp_op_req;
wire exp_irq;
//----------------------------------------
wire exp_drq_ip;
wire exp_drq_op;
wire [3:0] exp_irq;
wire exp_merged_irq;
assign exp_irq0 = exp_irq[0];
assign exp_irq1 = exp_irq[1];
assign exp_irq2 = exp_irq[2];
assign exp_irq3 = exp_irq[3];
//----------------------------------------
// Expansion Region "exp" instance
//----------------------------------------
`ifdef NANSOC_EXPANSION_REGION
nanosoc_exp #(.ADDRWIDTH(29)
) u_nanosoc_exp (
`ifdef NANOSOC_EXPANSION_REGION
nanosoc_acc_wrapper #(
.AHBADDRWIDTH(29),
.CFGNUMIRQ(4)
) u_nanosoc_exp_wrapper (
.HCLK (HCLK),
.HRESETn (HRESETn),
......@@ -860,8 +867,11 @@ nanosoc_exp #(.ADDRWIDTH(29)
.HREADYOUTS (HREADYOUT_exp),
.HRESPS (HRESP_exp),
.HRDATAS (HRDATA_exp),
.ip_data_req (exp_ip_req),
.op_data_req (exp_op_req)
.exp_drq_ip_o (exp_drq_ip),
.exp_dlast_ip_i(1'b0),
.exp_drq_op_o (exp_drq_op),
.exp_dlast_op_i(1'b0),
.exp_irq_o (exp_irq)
);
`else
// Default slave - if no expansion region
......@@ -876,6 +886,30 @@ nanosoc_exp #(.ADDRWIDTH(29)
);
assign HRDATA_exp = 32'heaedeaed; // Tie off Expansion Address Expansion Data
//nanosoc_exp_wrapper #(.AHBADDRWIDTH(29)
//) u_nanosoc_exp_wrapper (
// .HCLK (HCLK),
// .HRESETn (HRESETn),
//
// // Input slave port: 32 bit data bus interface
// .HSEL_i (HSEL_exp),
// .HADDR_i (HADDR_exp[28:0]),
// .HTRANS_i (HTRANS_exp),
// .HSIZE_i (HSIZE_exp),
// .HPROT_i (HPROT_exp),
// .HWRITE_i (HWRITE_exp),
// .HREADY_i (HREADYMUX_exp),
// .HWDATA_i (HWDATA_exp),
//
// .HREADYOUT_o (HREADYOUT_exp),
// .HRESP_o (HRESP_exp),
// .HRDATA_o (HRDATA_exp),
// .exp_drq_ip_o (exp_drq_ip),
// .exp_dlast_ip_i(1'b0),
// .exp_drq_op_o (exp_drq_op),
// .exp_dlast_op_i(1'b0),
// .exp_irq_o (exp_irq)
//);
`endif
assign HRUSER_exp = 2'b00;
......@@ -1262,8 +1296,8 @@ localparam AWRAM9 = ADDR_WIDTH_RAM; // Address width - to match RAM instance siz
wire [DMA_CHANNEL_NUM-1:0] dma230_req; // tie off signal.
wire [DMA_CHANNEL_NUM-1:0] dma230_tie0 = {DMA_CHANNEL_NUM{1'b0}};
assign dma230_req[0] = exp_ip_req;
assign dma230_req[1] = exp_op_req;
assign dma230_req[0] = exp_drq_ip;
assign dma230_req[1] = exp_drq_op;
// DMA done per channel
......
system/test_io/verilog/nanosoc_adp_manager.v
View file @ f68c3e62
......@@ -11,7 +11,7 @@
//`define ADPBASIC 1
`begin_keywords "1364-2001"
//`begin_keywords "1364-2001"
module nanosoc_adp_manager // AHB initiator interface
#(parameter PROMPT_CHAR = "]"
......@@ -181,8 +181,8 @@ endfunction
function [63:0] FNBuild_param64_byte;
input [63:0] param64;
input [7:0] byte;
FNBuild_param64_byte = {byte[7:0], param64[63:08]};
input [7:0] octet;
FNBuild_param64_byte = {octet[7:0], param64[63:08]};
endfunction
function [31:0] FNBuild_param32_hexdigit;
......@@ -221,8 +221,8 @@ endfunction
function [31:0] FNBuild_param32_byte;
input [31:0] param32;
input [7:0] byte;
FNBuild_param32_byte = {byte[7:0], param32[31:08]};
input [7:0] octet;
FNBuild_param32_byte = {octet[7:0], param32[31:08]};
endfunction
......@@ -453,8 +453,8 @@ input [3:0] nibble;
begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
endtask
task ADP_txchar_next; // output char
input [7:0] byte;
begin com_tx_req<= 1; com_tx_byte <= byte; end
input [7:0] octet;
begin com_tx_req<= 1; com_tx_byte <= octet; end
endtask
task com_rx_nxt; com_rx_ack <=1; endtask
......@@ -764,7 +764,7 @@ always @(posedge HCLK or negedge HRESETn)
endmodule
`end_keywords
//`end_keywords
////AHBLITE_ADPMASTER instancing
//ADPmaster
......
system/testcodes/aes128_tests/aes128.h 0 → 100644
View file @ f68c3e62
#ifndef _AES128_H_
#define _AES128_H_
#include <stdint.h>
// define the API addresses here.
#define AES128_BASE (0x60000000)
// byte address I/O buffers
#define AES128_BUF_SIZE (0x4000)
typedef struct {
__I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
__I uint32_t CORE_VERSION; /* 0x0008-000B */
uint32_t RESRV0C; /* 0x000C */
__IO uint32_t CTRL; /* 0x0010 */
__O uint32_t CTRL_SET; /* 0x0014 */
__O uint32_t CTRLL_CLR; /* 0x0018 */
__I uint32_t STATUS; /* 0x001c */
__IO uint32_t QUAL; /* 0x0020 */
uint32_t RESRV24[3]; /* 0x0024 - 2F*/
__IO uint32_t DRQ_MSK; /* 0x0030 */
__O uint32_t DRQ_MSK_SET; /* 0x0034 */
__O uint32_t DRQ_MSK_CLR; /* 0x0038 */
__I uint32_t DRQ_STATUS; /* 0x003C */
__IO uint32_t IRQ_MSK; /* 0x0040 */
__O uint32_t IRQ_MSK_SET; /* 0x0044 */
__O uint32_t IRQ_MSK_CLR; /* 0x0048 */
__I uint32_t IRQ_STATUS; /* 0x004C */
uint8_t RESRV50[AES128_BUF_SIZE - 0x50];/* 0x0050-0x3FFC (4096-20 words) */
__IO uint8_t KEY128[AES128_BUF_SIZE]; /* 0x4000-7FFF (0x3FFF is last alias) */
__IO uint8_t TXTIP128[AES128_BUF_SIZE]; /* 0x8000-BFFF (0x3FFF is last alias) */
__I uint8_t TXTOP128[AES128_BUF_SIZE]; /* 0xC000-FFFF (0x3FFF is last alias) */
} AES128_TypeDef;
#define AES128 ((AES128_TypeDef *) AES128_BASE )
#define AES_BLOCK_SIZE 16
#define AES_KEY_LEN_128 16
#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
#define AES128_CTRL_REG_WIDTH ( 8)
#define AES128_CTRL_BIT_MAX ( (CTRL_REG_WIDTH-1)
#define AES128_CTRL_KEY_REQ_BIT (1<<0)
#define AES128_CTRL_IP_REQ_BIT (1<<1)
#define AES128_CTRL_OP_REQ_BIT (1<<2)
#define AES128_CTRL_ERR_REQ_BIT (1<<3)
#define AES128_CTRL_BYPASS_BIT (1<<6)
#define AES128_CTRL_ENCODE_BIT (1<<7)
#define AES128_STAT_REG_WIDTH ( 8)
#define AES128_STAT_KEY_REQ_BIT (1<<0)
#define AES128_STAT_IP_REQ_BIT (1<<1)
#define AES128_STAT_OP_REQ_BIT (1<<2)
#define AES128_STAT_ERR_REQ_BIT (1<<3)
#define AES128_STAT_KEYOK_BIT (1<<4)
#define AES128_STAT_VALID_BIT (1<<5)
#define AES128_STAT_BYPASS_BIT (1<<6)
#define AES128_STAT_ENCODE_BIT (1<<7)
#define AES128_KEY_REQ_BIT (1<<0)
#define AES128_IP_REQ_BIT (1<<1)
#define AES128_OP_REQ_BIT (1<<2)
#define AES128_ERR_REQ_BIT (1<<3)
#define AES128_KEYOK_BIT (1<<4)
#define AES128_VALID_BIT (1<<5)
#define AES128_BYPASS_BIT (1<<6)
#define AES128_ENCODE_BIT (1<<7)
#endif // _AES128_H_
system/testcodes/aes128_tests/aes128_tests.c 0 → 100644
View file @ f68c3e62
This diff is collapsed.
system/testcodes/aes128_tests/dma_pl230_driver.c 0 → 100644
View file @ f68c3e62
#include <stdio.h>
#include <string.h>
#include "dma_pl230_driver.h"
#define DEBUG_PRINTF(...) do {} while(0);
//#define cpu_to_be32(__x) __x
//#define be32_to_cpu(__x) __x
#ifdef __cplusplus
extern "C" {
#endif
static int g_dma_pl230_initialised = 0;
static dma_pl230_data_structure priv_dma __attribute__((aligned(256)));
//
dma_pl230_data_structure *dma_pl230_table = &priv_dma;
/* --------------------------------------------------------------- */
/* Initialize DMA data structure */
/* --------------------------------------------------------------- */
void dma_pl230_data_struct_init(void)
{
int i; /* loop counter */
// printf ("dma structure block address = %x\n", dma_pl230_table);
for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
dma_pl230_table->Primary[i].SrcEndPointer = 0;
dma_pl230_table->Primary[i].DstEndPointer = 0;
dma_pl230_table->Primary[i].Control = 0;
dma_pl230_table->Alternate[i].SrcEndPointer = 0;
dma_pl230_table->Alternate[i].DstEndPointer = 0;
dma_pl230_table->Alternate[i].Control = 0;
}
g_dma_pl230_initialised = 1;
return;
}
void dma_pl230_data_struct_init_dbg(void)
{
int i; /* loop counter */
unsigned int ptr;
int ch_num; /* number of channels */
unsigned int blksize; /* Size of DMA data structure in bytes */
unsigned int blkmask; /* address mask */
ch_num = (((DMA_PL230_DMAC->DMA_STATUS) >> 16) & 0x1F)+1;
blksize = ch_num * 32;
if (ch_num > 16) blkmask = 0x3FF; /* 17 to 32 */
else if (ch_num > 8) blkmask = 0x1FF; /* 9 to 16 */
else if (ch_num > 4) blkmask = 0x0FF; /* 5 to 8 */
else if (ch_num > 2) blkmask = 0x07F; /* 3 to 4 */
else if (ch_num > 1) blkmask = 0x03F; /* 2 */
else blkmask = 0x01F; /* 1 */
/* Create DMA data structure in RAM after stack
In the linker script, a 1KB memory stack above stack is reserved
so we can use this space for putting the DMA data structure.
*/
// ptr = HW32_REG(0); /* Read Top of Stack */
ptr = (0x80000000); // force for now as no reserved RAM available
/* the DMA data structure must be aligned to the size of the data structure */
if ((ptr & blkmask) != 0x0)
ptr = (ptr + blksize) & ~blkmask;
/// if ((ptr + blksize) > (RAM_ADDRESS_MAX + 1)) {
/// puts ("ERROR : Not enough RAM space for DMA data structure.");
/// UartEndSimulation();
/// }
/* Set pointer to the reserved space */
dma_pl230_table = (dma_pl230_data_structure *) ptr;
ptr = (unsigned long) &(dma_pl230_table->Primary[0].SrcEndPointer);
printf ("dma structure block address = %x\n", ptr);
for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
dma_pl230_table->Primary[i].SrcEndPointer = 0;
dma_pl230_table->Primary[i].DstEndPointer = 0;
dma_pl230_table->Primary[i].Control = 0;
dma_pl230_table->Alternate[i].SrcEndPointer = 0;
dma_pl230_table->Alternate[i].DstEndPointer = 0;
dma_pl230_table->Alternate[i].Control = 0;
}
g_dma_pl230_initialised = 1;
return;
}
/* --------------------------------------------------------------- */
/* Initialize DMA PL230 */
/* --------------------------------------------------------------- */
void dma_pl230_init_dbg(unsigned int chan_mask)
{
unsigned int current_state;
puts ("Initialize PL230");
current_state = DMA_PL230_DMAC->DMA_STATUS;
printf ("- # of channels allowed : %d\n",(((current_state) >> 16) & 0x1F)+1);
/* Debugging printfs: */
printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
printf ("- Current master enable : %x\n",(((current_state) >> 0) & 0x1));
/* Wait until current DMA complete */
current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
if (!((current_state==0) || (current_state==0x8) || (current_state==0x9))) {
puts ("- wait for DMA IDLE/STALLED/DONE");
current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
}
while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
/* Wait if not IDLE/STALLED/DONE */
current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
}
DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
/* Set DMA data structure address */
DMA_PL230_DMAC->CHNL_ENABLE_CLR = 0xFFFFFFFF; /* Disable all channels */
DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
if (chan_mask)
DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
return;
}
void dma_pl230_init(unsigned int chan_mask)
{
unsigned int current_state;
if (g_dma_pl230_initialised ==0)
dma_pl230_data_struct_init();
/* Wait until current DMA complete */
current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
/* Wait if not IDLE/STALLED/DONE */
puts ("- wait for DMA IDLE/STALLED/DONE");
current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
}
DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
/* Set DMA data structure address */
DMA_PL230_DMAC->CHNL_ENABLE_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all channels */
DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
g_dma_pl230_initialised = 2;
if (chan_mask)
DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
return;
}
unsigned int dma_pl230_channel_active(unsigned int chan_mask)
{
return(DMA_PL230_DMAC->CHNL_ENABLE_SET & chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enabled channels */
}
#ifdef __cplusplus
}
#endif
system/testcodes/aes128_tests/dma_pl230_driver.h 0 → 100644
View file @ f68c3e62
#ifndef __DMA_PL230_MCU_H
#define __DMA_PL230_MCU_H
#ifdef __cplusplus
extern "C" {
#endif
#include "CMSDK_CM0.h"
#define DMA_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
#define MAX_NUM_OF_DMA_CHANNELS 2
/*------------- PL230 uDMA (PL230) --------------------------------------*/
/** @addtogroup DMA_PL230 CMSDK uDMA controller
@{
*/
typedef struct
{
__I uint32_t DMA_STATUS; /*!< Offset: 0x000 DMA status Register (R/W) */
__O uint32_t DMA_CFG; /*!< Offset: 0x004 DMA configuration Register ( /W) */
__IO uint32_t CTRL_BASE_PTR; /*!< Offset: 0x008 Channel Control Data Base Pointer Register (R/W) */
__I uint32_t ALT_CTRL_BASE_PTR; /*!< Offset: 0x00C Channel Alternate Control Data Base Pointer Register (R/ ) */
__I uint32_t DMA_WAITONREQ_STATUS; /*!< Offset: 0x010 Channel Wait On Request Status Register (R/ ) */
__O uint32_t CHNL_SW_REQUEST; /*!< Offset: 0x014 Channel Software Request Register ( /W) */
__IO uint32_t CHNL_USEBURST_SET; /*!< Offset: 0x018 Channel UseBurst Set Register (R/W) */
__O uint32_t CHNL_USEBURST_CLR; /*!< Offset: 0x01C Channel UseBurst Clear Register ( /W) */
__IO uint32_t CHNL_REQ_MASK_SET; /*!< Offset: 0x020 Channel Request Mask Set Register (R/W) */
__O uint32_t CHNL_REQ_MASK_CLR; /*!< Offset: 0x024 Channel Request Mask Clear Register ( /W) */
__IO uint32_t CHNL_ENABLE_SET; /*!< Offset: 0x028 Channel Enable Set Register (R/W) */
__O uint32_t CHNL_ENABLE_CLR; /*!< Offset: 0x02C Channel Enable Clear Register ( /W) */
__IO uint32_t CHNL_PRI_ALT_SET; /*!< Offset: 0x030 Channel Primary-Alterante Set Register (R/W) */
__O uint32_t CHNL_PRI_ALT_CLR; /*!< Offset: 0x034 Channel Primary-Alterante Clear Register ( /W) */
__IO uint32_t CHNL_PRIORITY_SET; /*!< Offset: 0x038 Channel Priority Set Register (R/W) */
__O uint32_t CHNL_PRIORITY_CLR; /*!< Offset: 0x03C Channel Priority Clear Register ( /W) */
uint32_t RESERVED0[3];
__IO uint32_t ERR_CLR; /*!< Offset: 0x04C Bus Error Clear Register (R/W) */
} DMA_PL230_TypeDef;
#define PL230_DMA_CHNL_BITS 0
#define DMA_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< DMA_PL230 DMA STATUS: MSTREN Position */
#define DMA_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_MSTREN_Pos) /*!< DMA_PL230 DMA STATUS: MSTREN Mask */
#define DMA_PL230_DMA_STATUS_STATE_Pos 0 /*!< DMA_PL230 DMA STATUS: STATE Position */
#define DMA_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << DMA_PL230_DMA_STATUS_STATE_Pos) /*!< DMA_PL230 DMA STATUS: STATE Mask */
#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Position */
#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
#define DMA_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< DMA_PL230 DMA STATUS: TEST_STATUS Position */
#define DMA_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< DMA_PL230 DMA STATUS: TEST_STATUS Mask */
#define DMA_PL230_DMA_CFG_MSTREN_Pos 0 /*!< DMA_PL230 DMA CFG: MSTREN Position */
#define DMA_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_CFG_MSTREN_Pos) /*!< DMA_PL230 DMA CFG: MSTREN Mask */
#define DMA_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< DMA_PL230 DMA CFG: CPCCACHE Position */
#define DMA_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCCACHE_Pos) /*!< DMA_PL230 DMA CFG: CPCCACHE Mask */
#define DMA_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< DMA_PL230 DMA CFG: CPCBUF Position */
#define DMA_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCBUF_Pos) /*!< DMA_PL230 DMA CFG: CPCBUF Mask */
#define DMA_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< DMA_PL230 DMA CFG: CPCPRIV Position */
#define DMA_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCPRIV_Pos) /*!< DMA_PL230 DMA CFG: CPCPRIV Mask */
#define DMA_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< DMA_PL230 STATUS: BASE_PTR Position */
#define DMA_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << DMA_PL230_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: BASE_PTR Mask */
#define DMA_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< DMA_PL230 STATUS: MSTREN Position */
#define DMA_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << DMA_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: MSTREN Mask */
#define DMA_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
#define DMA_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << DMA_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
#define DMA_PL230_CHNL_SW_REQUEST_Pos 0 /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
#define DMA_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_SW_REQUEST_Pos) /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
#define DMA_PL230_CHNL_USEBURST_SET_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: SET Position */
#define DMA_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_SET_Pos) /*!< DMA_PL230 CHNL_USEBURST: SET Mask */
#define DMA_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: CLR Position */
#define DMA_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_CLR_Pos) /*!< DMA_PL230 CHNL_USEBURST: CLR Mask */
#define DMA_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: SET Position */
#define DMA_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_SET_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: SET Mask */
#define DMA_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: CLR Position */
#define DMA_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: CLR Mask */
#define DMA_PL230_CHNL_ENABLE_SET_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: SET Position */
#define DMA_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_SET_Pos) /*!< DMA_PL230 CHNL_ENABLE: SET Mask */
#define DMA_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: CLR Position */
#define DMA_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_CLR_Pos) /*!< DMA_PL230 CHNL_ENABLE: CLR Mask */
#define DMA_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: SET Position */
#define DMA_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_SET_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: SET Mask */
#define DMA_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: CLR Position */
#define DMA_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: CLR Mask */
#define DMA_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: SET Position */
#define DMA_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_SET_Pos) /*!< DMA_PL230 CHNL_PRIORITY: SET Mask */
#define DMA_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: CLR Position */
#define DMA_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_CLR_Pos) /*!< DMA_PL230 CHNL_PRIORITY: CLR Mask */
#define DMA_PL230_ERR_CLR_Pos 0 /*!< DMA_PL230 ERR: CLR Position */
#define DMA_PL230_ERR_CLR_Msk (0x00000001ul << DMA_PL230_ERR_CLR_Pos) /*!< DMA_PL230 ERR: CLR Mask */
#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
/* Maximum to 32 DMA channel */
/* SRAM in example system is 64K bytes */
#define RAM_ADDRESS_MAX 0x80001fff
typedef struct /* 4 words */
{
volatile unsigned char* SrcEndPointer;
volatile unsigned char* DstEndPointer;
volatile unsigned long Control;
volatile unsigned long unused;
} dma_pl230_channel_data;
typedef struct /* 8 words per channel */
{ /* was one channel in the example uDMA setup */
volatile dma_pl230_channel_data Primary[MAX_NUM_OF_DMA_CHANNELS];
volatile dma_pl230_channel_data Alternate[MAX_NUM_OF_DMA_CHANNELS];
} dma_pl230_data_structure;
extern dma_pl230_data_structure *dma_pl230_table;
#define DMA_PL230_DMAC ((DMA_PL230_TypeDef *) DMA_PL230_BASE)
#define DMA_PL230_PTR_END(__ptr, __siz, __num) \
((unsigned char *) __ptr + ((1<<__siz)*(__num-1)))
#define DMA_PL230_CTRL(__cyc, __siz, __num, __rpwr) \
(((unsigned long) __siz << 30)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
(1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
(1 << 3)|(__cyc << 0) )
#define DMA_PL230_CTRL_SRCFIX(__cyc, __siz, __num, __rpwr) \
(((unsigned long) __siz << 30)|(__siz << 28)|(0x0c000000UL)|(__siz << 24)| \
(1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
(1 << 3)|(__cyc << 0) )
#define DMA_PL230_CTRL_DSTFIX(__cyc, __siz, __num, __rpwr) \
((0xc0000000UL)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
(1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
(1 << 3)|(__cyc << 0) )
#define DMA_PL230_MAX_XFERS (0x400)
#define PL230_CTRL_CYCLE_STOP 0
#define PL230_CTRL_CYCLE_BASIC 1
#define PL230_CTRL_CYCLE_AUTO 2
#define PL230_CTRL_CYCLE_PPONG 3
#define PL230_CTRL_CYCLE_MEM_CHAIN_PRI 4
#define PL230_CTRL_CYCLE_MEM_CHAIN_ALT 5
#define PL230_CTRL_CYCLE_DEV_CHAIN_PRI 6
#define PL230_CTRL_CYCLE_DEV_CHAIN_ALT 7
#define PL230_CTRL_RPWR_1 0
#define PL230_CTRL_RPWR_2 1
#define PL230_CTRL_RPWR_4 2
#define PL230_CTRL_RPWR_8 3
#define PL230_CTRL_RPWR_16 4
#define PL230_XFER_B 0
#define PL230_XFER_H 1
#define PL230_XFER_W 2
/* --------------------------------------------------------------- */
/* Initialize DMA data structure */
/* --------------------------------------------------------------- */
void dma_pl230_data_struct_init(void);
/* --------------------------------------------------------------- */
/* Initialize DMA PL230 */
/* --------------------------------------------------------------- */
void dma_pl230_init_dbg(unsigned int chan_mask);
void dma_pl230_init(unsigned int chan_mask);
/* --------------------------------------------------------------- */
/* Check DMA PL230 DMA channel(s) active (return 0 when finishes) */
/* --------------------------------------------------------------- */
unsigned int dma_pl230_channel_active(unsigned int chan_mask);
#ifdef __cplusplus
}
#endif
#endif /* __DMA_PL230_MCU_H */
system/testcodes/aes128_tests/makefile 0 → 100644
View file @ f68c3e62
#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#
# SVN Information
#
# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
#
# Revision : $Revision: 371321 $
#
# Release Information : Cortex-M System Design Kit-r1p1-00rel0
#-----------------------------------------------------------------------------
#
# Cortex-M System Design Kit software compilation make file
#
#-----------------------------------------------------------------------------
#
# Configurations
#
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = $(NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
else
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
endif
# Program file
TESTNAME = aes128_tests
# Endian Option
COMPILE_BIGEND = 0
# Configuration
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
USER_DEFINE = -DCORTEX_M0PLUS
else
USER_DEFINE = -DCORTEX_M0
endif
DEPS_LIST = makefile
# Tool chain : ds5 / gcc / keil
TOOL_CHAIN = ds5
ifeq ($(TOOL_CHAIN),ds5)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = --cpu Cortex-M0plus
else
CPU_TYPE = --cpu Cortex-M0
endif
endif
ifeq ($(TOOL_CHAIN),gcc)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = -mcpu=cortex-m0plus
else
CPU_TYPE = -mcpu=cortex-m0
endif
endif
# Startup code directory for DS-5
ifeq ($(TOOL_CHAIN),ds5)
STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
endif
# Startup code directory for gcc
ifeq ($(TOOL_CHAIN),gcc)
STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
STARTUP_FILE = startup_CMSDK_CM0plus
SYSTEM_FILE = system_CMSDK_CM0plus
else
STARTUP_FILE = startup_CMSDK_CM0
SYSTEM_FILE = system_CMSDK_CM0
endif
# ---------------------------------------------------------------------------------------
# DS-5 options
# MicroLIB option
COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
#ARM_ASM_OPTIONS = -g
#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
ARM_CC_OPTIONS += --bigend
ARM_ASM_OPTIONS += --bigend
ARM_LINK_OPTIONS += --be8
endif
ifeq ($(COMPILE_MICROLIB),1)
# MicroLIB
ARM_CC_OPTIONS += --library_type=microlib
ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
ARM_LINK_OPTIONS += --library_type=microlib
endif
ifeq ($(COMPILE_SMALLMUL),1)
# In Cortex-M0, small multiply takes 32 cycles
ARM_CC_OPTIONS += --multiply_latency=32
endif
# ---------------------------------------------------------------------------------------
# gcc options
GNG_CC = arm-none-eabi-gcc
GNU_OBJDUMP = arm-none-eabi-objdump
GNU_OBJCOPY = arm-none-eabi-objcopy
LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
GNU_CC_FLAGS += -mbig-endian
endif
# ---------------------------------------------------------------------------------------
all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# DS-5
all_ds5 : $(TESTNAME).hex $(TESTNAME).lst $(TESTNAME).bin
$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
dma_pl230_driver.o : dma_pl230_driver.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
$(TESTNAME).ELF : $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
$(TESTNAME).hex : $(TESTNAME).ELF
fromelf --vhx --8x1 $< --output $@
fromelf --vhx --8x1 $< --output ../../image.hex
$(TESTNAME).lst : $(TESTNAME).ELF
fromelf -c -d -e -s -z -v $< --output $@
$(TESTNAME).bin : $(TESTNAME).ELF
fromelf --bin $< --output $@
# ---------------------------------------------------------------------------------------
# gcc
all_gcc:
$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
$(TESTNAME).c \
$(SOFTWARE_DIR)/common/retarget/retarget.c \
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \
$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
# Generate disassembly code
$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
# Generate binary file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
# Generate hex file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
# Note:
# If the version of object copy you are using does not support verilog hex file output,
# you can generate the hex file from binary file using the following command
# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Keil MDK
all_keil:
@echo "Please compile your project code and press ENTER when ready"
@read dummy
# ---------------------------------------------------------------------------------------
# Binary
all_bin: $(TESTNAME).bin
# Generate hex file from binary
od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Clean
clean :
@rm -rf *.o
@if [ -e $(TESTNAME).hex ] ; then \
rm -rf $(TESTNAME).hex ; \
fi
@if [ -e $(TESTNAME).lst ] ; then \
rm -rf $(TESTNAME).lst ; \
fi
@if [ -e $(TESTNAME).ELF ] ; then \
rm -rf $(TESTNAME).ELF ; \
fi
@if [ -e $(TESTNAME).bin ] ; then \
rm -rf $(TESTNAME).bin ; \
fi
@rm -rf *.crf
@rm -rf *.plg
@rm -rf *.tra
@rm -rf *.htm
@rm -rf *.map
@rm -rf *.dep
@rm -rf *.d
@rm -rf *.lnp
@rm -rf *.bak
@rm -rf *.lst
@rm -rf *.axf
@rm -rf *.sct
@rm -rf *.__i
@rm -rf *._ia
system/verif/verilog/nanosoc_tb.v
View file @ f68c3e62
......@@ -37,6 +37,8 @@
//
`timescale 1ns/1ps
`define CORTEX_M0
module nanosoc_tb;
wire XTAL1; // crystal pin 1
......@@ -229,7 +231,7 @@ reg baud_clk_del;
wire uart_clk = (FASTMODE) ? PCLK : baud_clk; //(baud_clk & !baud_clk_del);
nanosoc_uart_capture #(.LOGFILENAME("uart2.log"))
nanosoc_uart_capture #(.LOGFILENAME("logs/uart2.log"))
u_nanosoc_uart_capture(
.RESETn (NRST),
.CLK (uart_clk), //PCLK),
......@@ -317,7 +319,7 @@ nanosoc_ft1248x1_to_axi_streamio_v1_0
);
nanosoc_axi_stream_io_8_rxd_to_file
#(.RXDFILENAME("ft1248_out.log"))
#(.RXDFILENAME("logs/ft1248_out.log"))
u_nanosoc_axi_stream_io_8_rxd_to_file
(
.aclk (XTAL1),
......@@ -358,7 +360,7 @@ nanosoc_ft1248x1_track
.FTDI_IP2UART_o (ft_txd2uart) // Transmitted data to UART capture
);
nanosoc_uart_capture #(.LOGFILENAME("ft1248_op.log"))
nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_op.log"))
u_nanosoc_uart_capture1(
.RESETn (NRST),
.CLK (ft_clk2uart),
......@@ -368,7 +370,7 @@ nanosoc_ft1248x1_track
.AUXCTRL ()
);
nanosoc_uart_capture #(.LOGFILENAME("ft1248_ip.log"))
nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_ip.log"))
u_nanosoc_uart_capture2(
.RESETn (NRST),
.CLK (ft_clk2uart),
......@@ -453,7 +455,7 @@ nanosoc_ft1248x1_track
.SE (`ARM_CM0IK_PATH.SE));
`define ARM_CM0IK_TRACK u_cortexm0_track
cm0_tarmac #(.LOGFILENAME("tarmac0.log"))
cm0_tarmac #(.LOGFILENAME("logs/tarmac0.log"))
u_tarmac_track
(.enable_i (1'b1),
......@@ -559,7 +561,7 @@ nanosoc_ft1248x1_track
`define DMAC_TRACK_PATH u_track_pl230_udma
nanosoc_dma_log_to_file #(.FILENAME("dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
nanosoc_dma_log_to_file #(.FILENAME("logs/dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
u_nanosoc_dma_log_to_file (
.hclk (`DMAC_TRACK_PATH.hclk),
.hresetn (`DMAC_TRACK_PATH.hresetn),
......@@ -595,33 +597,33 @@ nanosoc_ft1248x1_track
// Tracking AES logging support
// --------------------------------------------------------------------------------
// `define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_exp_aes128
// aes128_log_to_file #(.FILENAME("aes128.log"),.TIMESTAMP(1))
// u_aes_log_to_file (
// .ahb_hclk (`AES_PATH.ahb_hclk ),
// .ahb_hresetn (`AES_PATH.ahb_hresetn ),
// .ahb_hsel (`AES_PATH.ahb_hsel ),
// .ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
// .ahb_htrans (`AES_PATH.ahb_htrans ),
// .ahb_hwrite (`AES_PATH.ahb_hwrite ),
// .ahb_hsize (`AES_PATH.ahb_hsize ),
// .ahb_hprot (`AES_PATH.ahb_hprot ),
// .ahb_hwdata (`AES_PATH.ahb_hwdata ),
// .ahb_hready (`AES_PATH.ahb_hready ),
// .ahb_hrdata (`AES_PATH.ahb_hrdata ),
// .ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
// .ahb_hresp (`AES_PATH.ahb_hresp ),
// .drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
// .dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
// .drq_opdma128 (`AES_PATH.drq_opdma128 ),
// .dlast_opdma128 (`AES_PATH.dlast_opdma128),
// .irq_key128 (`AES_PATH.irq_key128 ),
// .irq_ip128 (`AES_PATH.irq_ip128 ),
// .irq_op128 (`AES_PATH.irq_op128 ),
// .irq_error (`AES_PATH.irq_error ),
// .irq_merged (`AES_PATH.irq_merged )
// );
`define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper.u_exp_aes128
aes128_log_to_file #(.FILENAME("logs/aes128.log"),.TIMESTAMP(1))
u_aes_log_to_file (
.ahb_hclk (`AES_PATH.ahb_hclk ),
.ahb_hresetn (`AES_PATH.ahb_hresetn ),
.ahb_hsel (`AES_PATH.ahb_hsel ),
.ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
.ahb_htrans (`AES_PATH.ahb_htrans ),
.ahb_hwrite (`AES_PATH.ahb_hwrite ),
.ahb_hsize (`AES_PATH.ahb_hsize ),
.ahb_hprot (`AES_PATH.ahb_hprot ),
.ahb_hwdata (`AES_PATH.ahb_hwdata ),
.ahb_hready (`AES_PATH.ahb_hready ),
.ahb_hrdata (`AES_PATH.ahb_hrdata ),
.ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
.ahb_hresp (`AES_PATH.ahb_hresp ),
.drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
.dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
.drq_opdma128 (`AES_PATH.drq_opdma128 ),
.dlast_opdma128 (`AES_PATH.dlast_opdma128),
.irq_key128 (`AES_PATH.irq_key128 ),
.irq_ip128 (`AES_PATH.irq_ip128 ),
.irq_op128 (`AES_PATH.irq_op128 ),
.irq_error (`AES_PATH.irq_error ),
.irq_merged (`AES_PATH.irq_merged )
);
// --------------------------------------------------------------------------------
......