nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v

@@ -149,7 +149,7 @@ module nanosoc_ss_dma #(
         .SYS_ADDR_W  (SYS_ADDR_W),
         .SYS_DATA_W  (SYS_DATA_W),
         .CFG_ADDR_W  (13),
-        .CHANNEL_NUM (DMAC_1_CHANNEL_NUM)
+        .CHANNEL_NUM (DMAC_0_CHANNEL_NUM)
     ) u_dmac (
         // AHB Clocks and Resets
         .HCLK(SYS_HCLK),

software/drivers/dma_350_command_lib.c

@@ -22,9 +22,9 @@
 #include "dma_350_command_lib.h"
 
 // Channel pointers
-DMACH_TypeDef *sec_dma_channels[2] =  { DMACH0_S,  DMACH1_S};
+DMACH_TypeDef *sec_dma_channels[3] =  { DMACH0_S,  DMACH1_S, DMACH2_S};
 
-DMACH_TypeDef *nsec_dma_channels[2] =  { DMACH0_NS,  DMACH1_NS};
+DMACH_TypeDef *nsec_dma_channels[3] =  { DMACH0_NS,  DMACH1_NS, DMACH2_NS};
 
 //
 // Get DMA channel register frame based on security and channel number

software/drivers/dma_350_command_lib.h

@@ -342,8 +342,8 @@
 
 // External variables
 // Channel pointers
-extern DMACH_TypeDef *sec_dma_channels[2];
-extern DMACH_TypeDef *nsec_dma_channels[2];
+extern DMACH_TypeDef *sec_dma_channels[3];
+extern DMACH_TypeDef *nsec_dma_channels[3];
 
 //Functions
 DMACH_TypeDef* GetChannelPtr(uint32_t ch_num, uint8_t security);

software/drivers/dma_350_regdef.h

@@ -164,7 +164,7 @@ typedef struct
 #define DMAINFO_S_BASE                              (ADA_DMA_S_BASE + 0x0F00UL)
 #define DMACH0_S_BASE                               (ADA_DMA_S_BASE + 0x1000UL)
 #define DMACH1_S_BASE                               (ADA_DMA_S_BASE + 0x1100UL)
-// #define DMACH2_S_BASE                               (ADA_DMA_S_BASE + 0x1200UL)
+#define DMACH2_S_BASE                               (ADA_DMA_S_BASE + 0x1200UL)
 // #define DMACH3_S_BASE                               (ADA_DMA_S_BASE + 0x1300UL)
 // #define DMACH4_S_BASE                               (ADA_DMA_S_BASE + 0x1400UL)
 // #define DMACH5_S_BASE                               (ADA_DMA_S_BASE + 0x1500UL)
@@ -181,7 +181,7 @@ typedef struct
 #define DMAINFO_NS_BASE                             (ADA_DMA_NS_BASE + 0x0F00UL)
 #define DMACH0_NS_BASE                              (ADA_DMA_NS_BASE + 0x1000UL)
 #define DMACH1_NS_BASE                              (ADA_DMA_NS_BASE + 0x1100UL)
-// #define DMACH2_NS_BASE                              (ADA_DMA_NS_BASE + 0x1200UL)
+#define DMACH2_NS_BASE                              (ADA_DMA_NS_BASE + 0x1200UL)
 // #define DMACH3_NS_BASE                              (ADA_DMA_NS_BASE + 0x1300UL)
 // #define DMACH4_NS_BASE                              (ADA_DMA_NS_BASE + 0x1400UL)
 // #define DMACH5_NS_BASE                              (ADA_DMA_NS_BASE + 0x1500UL)
@@ -197,7 +197,7 @@ typedef struct
 #define DMAINFO_S                                   ((DMAINFO_TypeDef *) DMAINFO_S_BASE)
 #define DMACH0_S                                    ((DMACH_TypeDef *) DMACH0_S_BASE)
 #define DMACH1_S                                    ((DMACH_TypeDef *) DMACH1_S_BASE)
-// #define DMACH2_S                                    ((DMACH_TypeDef *) DMACH2_S_BASE)
+#define DMACH2_S                                    ((DMACH_TypeDef *) DMACH2_S_BASE)
 // #define DMACH3_S                                    ((DMACH_TypeDef *) DMACH3_S_BASE)
 // #define DMACH4_S                                    ((DMACH_TypeDef *) DMACH4_S_BASE)
 // #define DMACH5_S                                    ((DMACH_TypeDef *) DMACH5_S_BASE)
@@ -210,7 +210,7 @@ typedef struct
 #define DMAINFO_NS                                  ((DMAINFO_TypeDef *) DMAINFO_NS_BASE)
 #define DMACH0_NS                                   ((DMACH_TypeDef *) DMACH0_NS_BASE)
 #define DMACH1_NS                                   ((DMACH_TypeDef *) DMACH1_NS_BASE)
-// #define DMACH2_NS                                   ((DMACH_TypeDef *) DMACH2_NS_BASE)
+#define DMACH2_NS                                   ((DMACH_TypeDef *) DMACH2_NS_BASE)
 // #define DMACH3_NS                                   ((DMACH_TypeDef *) DMACH3_NS_BASE)
 // #define DMACH4_NS                                   ((DMACH_TypeDef *) DMACH4_NS_BASE)
 // #define DMACH5_NS                                   ((DMACH_TypeDef *) DMACH5_NS_BASE)

testcodes/dma350_stream_tests/dma350_stream_tests.hex

-90
+98
 04
 00
 30
@@ -2066,19 +2066,19 @@ C1
 00
 00
 00
-90
+98
 00
 00
 30
-90
+98
 04
 00
 30
-90
+98
 02
 00
 30
-90
+98
 02
 00
 30
@@ -3254,7 +3254,7 @@ E0
 20
 31
 00
-28
+2C
 00
 00
 30
@@ -9678,7 +9678,7 @@ BD
 48
 70
 47
-38
+40
 00
 00
 30
@@ -10098,7 +10098,7 @@ D2
 48
 70
 47
-30
+38
 00
 00
 30
@@ -10710,7 +10710,7 @@ F0
 00
 00
 30
-30
+38
 00
 00
 00
@@ -10718,11 +10718,11 @@ F0
 01
 00
 00
-20
+28
 2A
 00
 00
-30
+38
 00
 00
 30
@@ -10775,6 +10775,10 @@ D1
 00
 40
 00
+D2
+00
+40
+00
 D0
 00
 40
@@ -10782,3 +10786,7 @@ D0
 D1
 00
 40
+00
+D2
+00
+40