doc/tex/nanosoc_configuration_manual.tex

@@ -220,6 +220,7 @@ To add your own testcodes to run on nanosoc in the simulation environment, you c
     \item Copy the makefile from one of the example testcodes to your test code directory
     \item Edit the TESTNAME variable in the new makefile to the name of your test
     \item If you want to run any ADP code before your test, add an adp.cmp file (example in the adp\_v4\_cmd\_tests)
+    \item If you want to preload expansion memories, add an expram\_l.hex and/or expram\_h.hex
     \item Add the name of your test to the accelerator-project/system/software\_list.txt file 
 \end{enumerate}
 
@@ -252,6 +253,18 @@ For more detailed C code templates, please see the firmware in the
 accelerator-project/nanosoc\_tech/software/common/validation.
 These are also the testcodes used for validating nanoSoC.
 
+\subsection{Preloading expansion memories}
+You may want to load test vectors directly into the expansion memories to run your tests. Doing this can save space in the 
+instruction memory space as you then don't have to load data in as arrays or vectors in your testcode. Instead you can use the simulator
+to automatically load these memories at the start of simulation.
+
+To do this, simply add an "expram\_l.hex" file and/or "expram\_h.hex" file to your testcode directory. These files will then 
+be loaded to the EXPRAM\_L or EXPRAM\_H region repectively. These can then be addressed in your testcode from 0x80000000 for EXPRAM\_L 
+and 0x90000000 for EXPRAM\_H. 
+
+The expram\_l.hex files must be ASCII text files with a single byte per line. They will look very similar to the .hex files that are used
+to preload the instruction memory.
+
 
 \chapter{FPGA Flow}
 \section{Summary}