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verif/tb/verilog/nanosoc_tb_qs.v
View file @ 236b65b9
......@@ -163,7 +163,8 @@ SROM_Ax32
pullup(P1[ 4]);
pullup(P1[ 5]);
pullup(P1[ 6]);
pullup(P1[ 7]);
// pullup(P1[ 7]);
pulldown(P1[ 7]);
pullup(P1[ 8]);
pullup(P1[ 9]);
pullup(P1[10]);
......@@ -173,6 +174,179 @@ SROM_Ax32
pullup(P1[14]);
pullup(P1[15]);
`ifdef FAST_SIM
parameter FAST_LOAD = 1;
`else
parameter FAST_LOAD = 0;
`endif
// --------------------------------------------------------------------------------
// EXTIO8x4 stream interface - enabled when P1[7] is low
// default in previous testbenches was pullup (for FT1248, UART2)
//
// v1 mapping was: v2 config
// P1[0] - ft_miso_in ioreq1
// P1[1] - ft_clk_out ioreq2
// P1[2] - ft_miosio_io ioack
// P1[3] - ft_ssn_out iodata[0]
// P1[4] - uart2_rxd iodata[1]
// P1[5] - uart2_txd iodata[2]
// P1[6] - reserved (1) iodata[3]
// P1[7] - reserved (1) zero
// --------------------------------------------------------------------------------
// 4-channel AXIS interface - Subordinate side
wire axis_rx0_tready;
wire axis_rx0_tvalid;
wire [7:0] axis_rx0_tdata8;
wire axis_rx1_tready;
wire axis_rx1_tvalid;
wire [7:0] axis_rx1_tdata8;
wire axis_tx0_tready;
wire axis_tx0_tvalid;
wire [7:0] axis_tx0_tdata8;
wire axis_tx1_tready;
wire axis_tx1_tvalid;
wire [7:0] axis_tx1_tdata8;
// external io interface
tri [3:0] iodata4;
wire [3:0] iodata4_i;
wire [3:0] iodata4_o;
wire [3:0] iodata4_e;
wire [3:0] iodata4_t;
wire ioreq1;
wire ioreq2;
wire ioack;
wire test_done;
wire FT1248MODE = P1[7];
wire end_sim = test_done & !FT1248MODE & !ioreq1 & !ioreq2 & !ioack;
always @(posedge PCLK)
if (end_sim) begin
$stop;
end
extio8x4_axis_target u_extio8x4_axis_target
(
.clk ( CLK ),
.resetn ( NRST ),
.testmode ( TEST ),
// RX 4-channel AXIS interface
.axis_rx0_tready ( axis_rx0_tready ),
.axis_rx0_tvalid ( axis_rx0_tvalid ),
.axis_rx0_tdata8 ( axis_rx0_tdata8 ),
.axis_rx1_tready ( axis_rx1_tready ),
.axis_rx1_tvalid ( axis_rx1_tvalid ),
.axis_rx1_tdata8 ( axis_rx1_tdata8 ),
.axis_tx0_tready ( axis_tx0_tready ),
.axis_tx0_tvalid ( axis_tx0_tvalid ),
.axis_tx0_tdata8 ( axis_tx0_tdata8 ),
.axis_tx1_tready ( axis_tx1_tready ),
.axis_tx1_tvalid ( axis_tx1_tvalid ),
.axis_tx1_tdata8 ( axis_tx1_tdata8 ),
// external io interface
.iodata4_i ( iodata4_i ),
.iodata4_o ( iodata4_o ),
.iodata4_e ( iodata4_e ),
.iodata4_t ( iodata4_t ),
.ioreq1_a ( ioreq1 ),
.ioreq2_a ( ioreq2 ),
.ioack_o ( ioack )
);
// tristate buffer emulation
assign ioreq1 = FT1248MODE ? 1'b0 : P1[0];
assign ioreq2 = FT1248MODE ? 1'b0 : P1[1];
bufif0 #1 (P1[2], ioack, FT1248MODE);
bufif0 #1 (P1[3], iodata4_o[0], (iodata4_t[0] | FT1248MODE));
bufif0 #1 (P1[4], iodata4_o[1], (iodata4_t[1] | FT1248MODE));
bufif0 #1 (P1[5], iodata4_o[2], (iodata4_t[2] | FT1248MODE));
bufif0 #1 (P1[6], iodata4_o[3], (iodata4_t[3] | FT1248MODE));
assign iodata4_i = {4{FT1248MODE}} | P1[6:3];
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME),
// .CODEFILENAME("null.hex"),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_adp_txd_from_file (
.aclk (CLK),
.aresetn (NRST),
.txd8_ready (axis_rx0_tready),
.txd8_valid (axis_rx0_tvalid),
.txd8_data (axis_rx0_tdata8)
);
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/extadp_in.log")
) u_nanosoc_axi_stream_io_8_adprxd_to_file (
.aclk (CLK),
.aresetn (NRST),
.eof_received ( ),
.rxd8_ready ( ), //axis_rx0_tready),
.rxd8_valid (axis_rx0_tvalid & axis_rx0_tready),
.rxd8_data (axis_rx0_tdata8)
);
`endif
/*
nanosoc_axi_stream_io_8_txd_from_file #(
.TXDFILENAME(ADP_FILENAME),
// .CODEFILENAME("null.hex"),
.FAST_LOAD(FAST_LOAD)
) u_nanosoc_axi_stream_io_dat_txd_from_file (
.aclk (CLK),
.aresetn (NRST),
.txd8_ready (axis_rx1_tready),
.txd8_valid (axis_rx1_tvalid),
.txd8_data (axis_rx1_tdata8)
);
*/
nanosoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/extadp_out.log"),
.VERBOSE(0)
) u_nanosoc_axi_stream_io_stream_adp_rxd_to_file (
.aclk (CLK),
.aresetn (NRST),
.eof_received (test_done),
.rxd8_ready (axis_tx0_tready),
.rxd8_valid (axis_tx0_tvalid),
.rxd8_data (axis_tx0_tdata8)
);
soclabs_axis8_capture #(.LOGFILENAME("logs/extio_adp_out.log"))
u_soclabs_axis8_capture1(
.RESETn (NRST),
.CLK (CLK),
.RXD8_READY ( ),
.RXD8_VALID (axis_tx0_tvalid & axis_tx0_tready),
.RXD8_DATA (axis_tx0_tdata8),
.DEBUG_TESTER_ENABLE ( ),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
nanosoc_axi_stream_io_8_rxd_to_file#(
.RXDFILENAME("logs/extdat_out.log")
) u_nanosoc_axi_stream_io_extdata_8_rxd_to_file (
.aclk (CLK),
.aresetn (NRST),
.eof_received ( ),
.rxd8_ready ( ), //axis_tx1_tready),
.rxd8_valid (axis_tx1_tvalid & axis_tx1_tready),
.rxd8_data (axis_tx1_tdata8)
);
assign axis_tx1_tready = axis_rx1_tready;
assign axis_rx1_tvalid = axis_tx1_tvalid;
assign axis_rx1_tdata8 = axis_tx1_tdata8;
`endif
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
......@@ -271,12 +445,35 @@ reg baud_clk_del;
// assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
// assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
assign P1[4] = P1[5]; // loopback UART2
// --------------------------------------------------------------------------------
// FTDI IO capture
// --------------------------------------------------------------------------------
// UART connection
/// assign P1[4] = P1[5]; // loopback UART2
wire ft_clk_out = P1[1];
bufif1 #1 (P1[4], P1[5], FT1248MODE);
/// wire ft_clk_out = P1[1];
/// wire ft_miso_in;
/// assign P1[0] = ft_miso_in;
/// wire ft_ssn_out = P1[3];
wire ft_clk_out;
wire ft_miso_in;
assign P1[0] = ft_miso_in;
wire ft_ssn_out = P1[3];
wire ft_ssn_out;
assign ft_clk_out = (FT1248MODE) ? P1[1] : 1'b0;
bufif1 #1 (P1[0], ft_miso_in, FT1248MODE);
assign ft_ssn_out = (FT1248MODE) ? P1[3] : 1'b1;
wire ft_miosio_o;
wire ft_miosio_z;
wire ft_miosio_i;
/// assign ft_miosio_i = P1[2]; // & ft_miosio_z;
/// assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
assign ft_miosio_i = (FT1248MODE) ? P1[2] : 1'b0; // & ft_miosio_z;
bufif1 #1 (P1[2], ft_miosio_o, (FT1248MODE & !ft_miosio_z));
//
// AXI stream io testing
......@@ -290,11 +487,6 @@ reg baud_clk_del;
wire rxd8_tvalid;
wire [7:0] rxd8_tdata ;
`ifdef FAST_SIM
parameter FAST_LOAD = 1;
`else
parameter FAST_LOAD = 0;
`endif
`ifndef COCOTB_SIM
nanosoc_axi_stream_io_8_txd_from_file #(
......@@ -309,10 +501,6 @@ reg baud_clk_del;
);
`endif
wire ft_miosio_o;
wire ft_miosio_z;
wire ft_miosio_i = P1[2]; // & ft_miosio_z;
assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
nanosoc_ft1248x1_to_axi_streamio_v1_0 u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
......