Skip to content
GitLab
Explore
Sign in
Register
Primary navigation
Search or go to…
Project
NanoSoC Tech
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Jira
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Deploy
Releases
Package registry
Model registry
Operate
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
SoCLabs
NanoSoC Tech
Compare revisions
236b65b93b7326d2c922d4a2e854dad440963f32 to f4fc40f3a4c13d9e140d5f5ade3127edb71c14ed
Compare revisions
Changes are shown as if the
source
revision was being merged into the
target
revision.
Learn more about comparing revisions.
Source
soclabs/nanosoc_tech
Select target project
No results found
f4fc40f3a4c13d9e140d5f5ade3127edb71c14ed
Select Git revision
Swap
Target
soclabs/nanosoc_tech
Select target project
soclabs/nanosoc_tech
1 result
236b65b93b7326d2c922d4a2e854dad440963f32
Select Git revision
Show changes
Only incoming changes from source
Include changes to target since source was created
Compare
Commits on Source (1)
zcu104 target extio testbench
· f4fc40f3
dwf1m12
authored
7 months ago
f4fc40f3
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
+992
-192
992 additions, 192 deletions
...rgets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
with
992 additions
and
192 deletions
fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl
View file @
f4fc40f3
################################################################
# This is a generated script based on design:
design_1
# This is a generated script based on design:
extio8x4_io
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
...
...
@@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
################################################################
# To test this script, run the following commands from Vivado Tcl console:
# source
design_1
_script.tcl
# source
extio8x4_io
_script.tcl
set bCheckIPsPassed 1
##################################################################
...
...
@@ -46,17 +46,13 @@ if { $bCheckIPs == 1 } {
set list_check_ips
"
\
soclabs.org:user:nanosoc_chip:1.0
\
xilinx.com:ip:zynq_ultra_ps_e:3.3
\
soclabs.org:user:ADPcontrol:1.0
\
xilinx.com:ip:ahblite_axi_bridge:3.0
\
xilinx.com:ip:axi_bram_ctrl:4.1
\
xilinx.com:ip:axi_gpio:2.0
\
soclabs.org:user:axi_stream_io:1.0
\
xilinx.com:ip:axi_uartlite:2.0
\
xilinx.com:ip:axis_data_fifo:2.0
\
xilinx.com:ip:blk_mem_gen:8.4
\
soclabs.org:user:ft1248x1_to_axi_streamio:1.0
\
xilinx.com:ip:xlslice:1.0
\
soclabs.org:slip:extio8x4_axis_target:1.0
\
xilinx.com:ip:xlconcat:2.1
\
xilinx.com:ip:xlslice:1.0
\
xilinx.com:ip:proc_sys_reset:5.0
\
xilinx.com:ip:smartconnect:1.0
\
xilinx.com:ip:xlconstant:1.1
\
...
...
@@ -134,7 +130,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
create_bd_pin -dir O -from 15 -to 0 p0_tri_i
create_bd_pin -dir I -from 15 -to 0 p0_tri_o
create_bd_pin -dir I -from 15 -to 0 p0_tri_z
create_bd_pin -dir O -from
15
-to 0 p1_tri_i
create_bd_pin -dir O -from
7
-to 0 p1_tri_i
create_bd_pin -dir I -from 15 -to 0 p1_tri_o
create_bd_pin -dir I -from 15 -to 0 p1_tri_z
create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
...
...
@@ -145,20 +141,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
create_bd_pin -dir I swdio_tri_o
create_bd_pin -dir I swdio_tri_z
# Create instance: ADPcontrol_0, and set properties
set ADPcontrol_0
[
create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0
]
# Create instance: ahblite_axi_bridge_0, and set properties
set ahblite_axi_bridge_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0
]
# Create instance: axi_bram_ctrl_0, and set properties
set axi_bram_ctrl_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0
]
set_property -dict
[
list
\
CONFIG.ECC_TYPE
{
Hamming
}
\
CONFIG.PROTOCOL
{
AXI4
}
\
CONFIG.SINGLE_PORT_BRAM
{
1
}
\
]
$axi_bram_ctrl_0
# Create instance: axi_gpio_0, and set properties
set axi_gpio_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0
]
set_property -dict
[
list
\
...
...
@@ -205,144 +187,57 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.FIFO_DEPTH
{
64
}
\
]
$axis_data_fifo_0
# Create instance: axis_data_fifo_1, and set properties
set axis_data_fifo_1
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1
]
set_property -dict
[
list
\
CONFIG.FIFO_DEPTH
{
64
}
\
]
$axis_data_fifo_1
# Create instance: axis_data_fifo_2, and set properties
set axis_data_fifo_2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2
]
set_property -dict
[
list
\
CONFIG.FIFO_DEPTH
{
64
}
\
]
$axis_data_fifo_2
# Create instance: axis_data_fifo_3, and set properties
set axis_data_fifo_3
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3
]
set_property -dict
[
list
\
CONFIG.FIFO_DEPTH
{
64
}
\
]
$axis_data_fifo_3
# Create instance: axis_data_fifo_4, and set properties
set axis_data_fifo_4
[
create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4
]
set_property -dict
[
list
\
CONFIG.FIFO_DEPTH
{
64
}
\
]
$axis_data_fifo_4
# Create instance: extio8x4_axis_target_0, and set properties
set extio8x4_axis_target_0
[
create_bd_cell -type ip -vlnv soclabs.org:slip:extio8x4_axis_target:1.0 extio8x4_axis_target_0
]
# Create instance: blk_mem_gen_0, and set properties
set blk_mem_gen_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0
]
set_property -dict
[
list
\
CONFIG.Byte_Size
{
8
}
\
CONFIG.EN_SAFETY_CKT
{
true
}
\
CONFIG.Enable_32bit_Address
{
true
}
\
CONFIG.Read_Width_A
{
32
}
\
CONFIG.Read_Width_B
{
32
}
\
CONFIG.Register_PortA_Output_of_Memory_Primitives
{
false
}
\
CONFIG.Use_Byte_Write_Enable
{
true
}
\
CONFIG.Use_RSTA_Pin
{
true
}
\
CONFIG.Write_Width_A
{
32
}
\
CONFIG.Write_Width_B
{
32
}
\
CONFIG.use_bram_block
{
BRAM_Controller
}
\
]
$blk_mem_gen_0
# Create instance: ft1248x1_to_axi_stream_0, and set properties
set ft1248x1_to_axi_stream_0
[
create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0
]
# Create instance: p1_i_bit15to8, and set properties
set p1_i_bit15to8
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to8
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
15
}
\
CONFIG.DIN_TO
{
8
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
8
}
\
]
$p1_i_bit15to8
# Create instance: p1_i_concat, and set properties
set p1_i_concat
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat
]
# Create instance: p1_extio_concat_o, and set properties
set p1_extio_concat_o
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_extio_concat_o
]
set_property -dict
[
list
\
CONFIG.IN0_WIDTH
{
1
}
\
CONFIG.IN1_WIDTH
{
1
}
\
CONFIG.IN2_WIDTH
{
1
}
\
CONFIG.IN3_WIDTH
{
1
}
\
CONFIG.IN3_WIDTH
{
4
}
\
CONFIG.IN4_WIDTH
{
1
}
\
CONFIG.IN5_WIDTH
{
1
}
\
CONFIG.IN6_WIDTH
{
1
}
\
CONFIG.IN7_WIDTH
{
1
}
\
CONFIG.IN8_WIDTH
{
8
}
\
CONFIG.NUM_PORTS
{
9
}
\
]
$p1_i_concat
# Create instance: p1_o_bit1, and set properties
set p1_o_bit1
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
1
}
\
CONFIG.DIN_TO
{
1
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p1_o_bit1
CONFIG.NUM_PORTS
{
5
}
\
]
$p1_extio_concat_o
# Create instance: p1_
o_bit15to6
, and set properties
set p1_
o_bit15to6
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xl
slice:1.0 p1_o_bit15to6
]
# Create instance: p1_
extio_concat_z
, and set properties
set p1_
extio_concat_z
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xl
concat:2.1 p1_extio_concat_z
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
15
}
\
CONFIG.DIN_TO
{
6
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
10
}
\
]
$p1_o_bit15to6
# Create instance: p1_o_bit2, and set properties
set p1_o_bit2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
2
}
\
CONFIG.DIN_TO
{
2
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p1_o_bit2
# Create instance: p1_o_bit3, and set properties
set p1_o_bit3
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
3
}
\
CONFIG.DIN_TO
{
3
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p1_o_bit3
CONFIG.IN0_WIDTH
{
1
}
\
CONFIG.IN1_WIDTH
{
1
}
\
CONFIG.IN2_WIDTH
{
1
}
\
CONFIG.IN3_WIDTH
{
4
}
\
CONFIG.IN4_WIDTH
{
1
}
\
CONFIG.NUM_PORTS
{
5
}
\
]
$p1_extio_concat_z
# Create instance: p1_o_bit
5
, and set properties
set p1_o_bit
5
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit
5
]
# Create instance: p1_o_bit
0_ioreq1
, and set properties
set p1_o_bit
0_ioreq1
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit
0_ioreq1
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
5
}
\
CONFIG.DIN_TO
{
5
}
\
CONFIG.DIN_FROM
{
0
}
\
CONFIG.DIN_TO
{
0
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p1_o_bit
5
]
$p1_o_bit
0_ioreq1
# Create instance: p1_
z
_bit2, and set properties
set p1_
z
_bit2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_
z
_bit2
]
# Create instance: p1_
o
_bit
1_ioreq
2, and set properties
set p1_
o
_bit
1_ioreq
2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_
o
_bit
1_ioreq
2
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
2
}
\
CONFIG.DIN_TO
{
2
}
\
CONFIG.DIN_FROM
{
1
}
\
CONFIG.DIN_TO
{
1
}
\
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p1_z_bit2
# Create instance: pmoda_i_bit2, and set properties
set pmoda_i_bit2
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
2
}
\
CONFIG.DIN_TO
{
2
}
\
CONFIG.DIN_WIDTH
{
8
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$pmoda_i_bit2
]
$p1_o_bit1_ioreq2
# Create instance: p
moda_i_bit3
, and set properties
set p
moda_i_bit3
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p
moda_i_bit3
]
# Create instance: p
1_o_bit3_iodatata4
, and set properties
set p
1_o_bit3_iodatata4
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p
1_o_bit3_iodatata4
]
set_property -dict
[
list
\
CONFIG.DIN_FROM
{
3
}
\
CONFIG.DIN_FROM
{
6
}
\
CONFIG.DIN_TO
{
3
}
\
CONFIG.DIN_WIDTH
{
8
}
\
CONFIG.DOUT_WIDTH
{
1
}
\
]
$p
moda_i_bit3
CONFIG.DIN_WIDTH
{
16
}
\
CONFIG.DOUT_WIDTH
{
4
}
\
]
$p
1_o_bit3_iodatata4
# Create instance: pmoda_i_bit4, and set properties
set pmoda_i_bit4
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4
]
...
...
@@ -362,12 +257,6 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
CONFIG.DOUT_WIDTH
{
1
}
\
]
$pmoda_i_bit7
# Create instance: pmoda_o_concat8, and set properties
set pmoda_o_concat8
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8
]
set_property -dict
[
list
\
CONFIG.NUM_PORTS
{
8
}
\
]
$pmoda_o_concat8
# Create instance: pmoda_z_concat8, and set properties
set pmoda_z_concat8
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8
]
set_property -dict
[
list
\
...
...
@@ -394,21 +283,13 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
set xlconstant_1
[
create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1
]
# Create interface connections
connect_bd_intf_net -intf_net ADPcontrol_0_ahb
[
get_bd_intf_pins ADPcontrol_0/ahb
]
[
get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE
]
connect_bd_intf_net -intf_net ADPcontrol_0_com_tx
[
get_bd_intf_pins ADPcontrol_0/com_tx
]
[
get_bd_intf_pins axis_data_fifo_3/S_AXIS
]
connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx
[
get_bd_intf_pins ADPcontrol_0/stdio_tx
]
[
get_bd_intf_pins axis_data_fifo_4/S_AXIS
]
connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI
[
get_bd_intf_pins ahblite_axi_bridge_0/M_AXI
]
[
get_bd_intf_pins axi_bram_ctrl_0/S_AXI
]
connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA
[
get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA
]
[
get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA
]
connect_bd_intf_net -intf_net axi_stream_io_0_tx
[
get_bd_intf_pins axi_stream_io_0/tx
]
[
get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8
]
connect_bd_intf_net -intf_net axi_stream_io_0_tx
[
get_bd_intf_pins axi_stream_io_0/tx
]
[
get_bd_intf_pins extio8x4_axis_target_0/axis_rx0
]
connect_bd_intf_net -intf_net axi_stream_io_1_tx
[
get_bd_intf_pins axi_stream_io_1/rx
]
[
get_bd_intf_pins axi_stream_io_1/tx
]
connect_bd_intf_net -intf_net axi_stream_io_2_tx
[
get_bd_intf_pins axi_stream_io_2/
t
x
]
[
get_bd_intf_pins axi
s_data_fifo_1/S_AXIS
]
connect_bd_intf_net -intf_net axi_stream_io_3_tx
[
get_bd_intf_pins axi_stream_io_3/
t
x
]
[
get_bd_intf_pins axi
s_data_fifo_2/S_AXIS
]
connect_bd_intf_net -intf_net axi_stream_io_2_tx
[
get_bd_intf_pins axi_stream_io_2/
r
x
]
[
get_bd_intf_pins axi
_stream_io_2/tx
]
connect_bd_intf_net -intf_net axi_stream_io_3_tx
[
get_bd_intf_pins axi_stream_io_3/
r
x
]
[
get_bd_intf_pins axi
_stream_io_3/tx
]
connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS
[
get_bd_intf_pins axi_stream_io_0/rx
]
[
get_bd_intf_pins axis_data_fifo_0/M_AXIS
]
connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS
[
get_bd_intf_pins axi_stream_io_2/rx
]
[
get_bd_intf_pins axis_data_fifo_1/M_AXIS
]
connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS
[
get_bd_intf_pins ADPcontrol_0/com_rx
]
[
get_bd_intf_pins axis_data_fifo_2/M_AXIS
]
connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS
[
get_bd_intf_pins axi_stream_io_3/rx
]
[
get_bd_intf_pins axis_data_fifo_3/M_AXIS
]
connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS
[
get_bd_intf_pins ADPcontrol_0/stdio_rx
]
[
get_bd_intf_pins axis_data_fifo_4/M_AXIS
]
connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8
[
get_bd_intf_pins axis_data_fifo_0/S_AXIS
]
[
get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8
]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx0
[
get_bd_intf_pins axis_data_fifo_0/S_AXIS
]
[
get_bd_intf_pins extio8x4_axis_target_0/axis_tx0
]
connect_bd_intf_net -intf_net extio8x4_axis_target_0_axis_tx1
[
get_bd_intf_pins extio8x4_axis_target_0/axis_rx1
]
[
get_bd_intf_pins extio8x4_axis_target_0/axis_tx1
]
connect_bd_intf_net -intf_net smartconnect_0_M00_AXI
[
get_bd_intf_pins axi_gpio_0/S_AXI
]
[
get_bd_intf_pins smartconnect_0/M00_AXI
]
connect_bd_intf_net -intf_net smartconnect_0_M01_AXI
[
get_bd_intf_pins axi_gpio_1/S_AXI
]
[
get_bd_intf_pins smartconnect_0/M01_AXI
]
connect_bd_intf_net -intf_net smartconnect_0_M02_AXI
[
get_bd_intf_pins axi_uartlite_0/S_AXI
]
[
get_bd_intf_pins smartconnect_0/M02_AXI
]
...
...
@@ -420,44 +301,29 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD
[
get_bd_intf_pins S00_AXI
]
[
get_bd_intf_pins smartconnect_0/S00_AXI
]
# Create port connections
connect_bd_net -net ADPcontrol_0_gpo8
[
get_bd_pins ADPcontrol_0/gpi8
]
[
get_bd_pins ADPcontrol_0/gpo8
]
connect_bd_net -net UART2_TXD
[
get_bd_pins axi_uartlite_0/rx
]
[
get_bd_pins p1_o_bit5/Dout
]
connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out
[
get_bd_pins ADPcontrol_0/ahb_hready
]
[
get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in
]
[
get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out
]
connect_bd_net -net axi_bram_ctrl_0_bram_addr_a
[
get_bd_pins axi_bram_ctrl_0/bram_addr_a
]
[
get_bd_pins blk_mem_gen_0/addra
]
connect_bd_net -net axi_bram_ctrl_0_bram_clk_a
[
get_bd_pins axi_bram_ctrl_0/bram_clk_a
]
[
get_bd_pins blk_mem_gen_0/clka
]
connect_bd_net -net axi_bram_ctrl_0_bram_en_a
[
get_bd_pins axi_bram_ctrl_0/bram_en_a
]
[
get_bd_pins blk_mem_gen_0/ena
]
connect_bd_net -net axi_bram_ctrl_0_bram_we_a
[
get_bd_pins axi_bram_ctrl_0/bram_we_a
]
[
get_bd_pins blk_mem_gen_0/wea
]
connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a
[
get_bd_pins axi_bram_ctrl_0/bram_wrdata_a
]
[
get_bd_pins blk_mem_gen_0/dina
]
connect_bd_net -net axi_gpio_0_gpio_io_o
[
get_bd_pins p0_tri_i
]
[
get_bd_pins axi_gpio_0/gpio_io_o
]
connect_bd_net -net axi_gpio_1_gpio_io_o
[
get_bd_pins axi_gpio_1/gpio_io_o
]
[
get_bd_pins p1_i_bit15to8/Din
]
connect_bd_net -net axi_uartlite_0_tx
[
get_bd_pins axi_uartlite_0/tx
]
[
get_bd_pins p1_i_concat/In4
]
connect_bd_net -net axi_uartlite_0_tx
[
get_bd_pins axi_uartlite_0/rx
]
[
get_bd_pins axi_uartlite_0/tx
]
connect_bd_net -net axi_uartlite_1_tx
[
get_bd_pins axi_uartlite_1/rx
]
[
get_bd_pins axi_uartlite_1/tx
]
connect_bd_net -net blk_mem_gen_0_douta
[
get_bd_pins axi_bram_ctrl_0/bram_rddata_a
]
[
get_bd_pins blk_mem_gen_0/douta
]
connect_bd_net -net cmsdk_mcu_chip_0_p0_o
[
get_bd_pins p0_tri_o
]
[
get_bd_pins axi_gpio_0/gpio_io_i
]
connect_bd_net -net cmsdk_mcu_chip_0_p0_z
[
get_bd_pins p0_tri_z
]
[
get_bd_pins axi_gpio_0/gpio2_io_i
]
connect_bd_net -net cmsdk_mcu_chip_0_p1_o
[
get_bd_pins p1_tri_o
]
[
get_bd_pins axi_gpio_1/gpio_io_i
]
[
get_bd_pins p1_o_bit1/Din
]
[
get_bd_pins p1_o_bit15to6/Din
]
[
get_bd_pins p1_o_bit2/Din
]
[
get_bd_pins p1_o_bit3/Din
]
[
get_bd_pins p1_o_bit5/Din
]
connect_bd_net -net const0
[
get_bd_pins p1_i_concat/In1
]
[
get_bd_pins p1_i_concat/In3
]
[
get_bd_pins p1_i_concat/In5
]
[
get_bd_pins p1_i_concat/In6
]
[
get_bd_pins pmoda_o_concat8/In2
]
[
get_bd_pins pmoda_o_concat8/In5
]
[
get_bd_pins pmoda_o_concat8/In6
]
[
get_bd_pins pmoda_o_concat8/In7
]
[
get_bd_pins pmoda_z_concat8/In0
]
[
get_bd_pins pmoda_z_concat8/In1
]
[
get_bd_pins xlconstant_0/dout
]
connect_bd_net -net const1
[
get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel
]
[
get_bd_pins p1_i_concat/In7
]
[
get_bd_pins pmoda_z_concat8/In2
]
[
get_bd_pins pmoda_z_concat8/In5
]
[
get_bd_pins pmoda_z_concat8/In6
]
[
get_bd_pins pmoda_z_concat8/In7
]
[
get_bd_pins xlconstant_1/dout
]
connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o
[
get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o
]
[
get_bd_pins p1_i_concat/In2
]
connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o
[
get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o
]
[
get_bd_pins p1_i_concat/In0
]
connect_bd_net -net ftclk_o
[
get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i
]
[
get_bd_pins p1_o_bit1/Dout
]
[
get_bd_pins pmoda_o_concat8/In0
]
connect_bd_net -net ftmiosio_o
[
get_bd_pins p1_o_bit2/Dout
]
[
get_bd_pins pmoda_o_concat8/In3
]
connect_bd_net -net ftmiosio_z
[
get_bd_pins p1_z_bit2/Dout
]
[
get_bd_pins pmoda_z_concat8/In3
]
connect_bd_net -net ftssn_n
[
get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i
]
[
get_bd_pins p1_o_bit3/Dout
]
[
get_bd_pins pmoda_o_concat8/In1
]
connect_bd_net -net p1_i
[
get_bd_pins p1_tri_i
]
[
get_bd_pins p1_i_concat/dout
]
connect_bd_net -net p1_i_bit15to8_Dout
[
get_bd_pins p1_i_bit15to8/Dout
]
[
get_bd_pins p1_i_concat/In8
]
connect_bd_net -net p1_z
[
get_bd_pins p1_tri_z
]
[
get_bd_pins axi_gpio_1/gpio2_io_i
]
[
get_bd_pins p1_z_bit2/Din
]
connect_bd_net -net pmoda_i_1
[
get_bd_pins pmoda_tri_i
]
[
get_bd_pins pmoda_i_bit2/Din
]
[
get_bd_pins pmoda_i_bit3/Din
]
[
get_bd_pins pmoda_i_bit4/Din
]
[
get_bd_pins pmoda_i_bit7/Din
]
connect_bd_net -net pmoda_i_bit3_Dout
[
get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i
]
[
get_bd_pins pmoda_i_bit3/Dout
]
connect_bd_net -net cmsdk_mcu_chip_0_p1_o
[
get_bd_pins p1_tri_o
]
[
get_bd_pins axi_gpio_1/gpio_io_i
]
[
get_bd_pins p1_o_bit0_ioreq1/Din
]
[
get_bd_pins p1_o_bit1_ioreq2/Din
]
[
get_bd_pins p1_o_bit3_iodatata4/Din
]
connect_bd_net -net const0
[
get_bd_pins extio8x4_axis_target_0/testmode
]
[
get_bd_pins p1_extio_concat_o/In0
]
[
get_bd_pins p1_extio_concat_o/In1
]
[
get_bd_pins p1_extio_concat_o/In4
]
[
get_bd_pins p1_extio_concat_z/In2
]
[
get_bd_pins p1_extio_concat_z/In4
]
[
get_bd_pins pmoda_z_concat8/In0
]
[
get_bd_pins pmoda_z_concat8/In1
]
[
get_bd_pins pmoda_z_concat8/In2
]
[
get_bd_pins pmoda_z_concat8/In3
]
[
get_bd_pins pmoda_z_concat8/In4
]
[
get_bd_pins pmoda_z_concat8/In5
]
[
get_bd_pins pmoda_z_concat8/In6
]
[
get_bd_pins pmoda_z_concat8/In7
]
[
get_bd_pins xlconstant_0/dout
]
connect_bd_net -net const1
[
get_bd_pins p1_extio_concat_z/In0
]
[
get_bd_pins p1_extio_concat_z/In1
]
[
get_bd_pins xlconstant_1/dout
]
connect_bd_net -net extio8x4_axis_target_0_ioack_o
[
get_bd_pins extio8x4_axis_target_0/ioack_o
]
[
get_bd_pins p1_extio_concat_o/In2
]
connect_bd_net -net extio8x4_axis_target_0_iodata4_o
[
get_bd_pins extio8x4_axis_target_0/iodata4_o
]
[
get_bd_pins p1_extio_concat_o/In3
]
connect_bd_net -net extio8x4_axis_target_0_iodata4_t
[
get_bd_pins extio8x4_axis_target_0/iodata4_t
]
[
get_bd_pins p1_extio_concat_z/In3
]
connect_bd_net -net p1_extio_concat_o_dout
[
get_bd_pins p1_tri_i
]
[
get_bd_pins pmoda_tri_o
]
[
get_bd_pins p1_extio_concat_o/dout
]
connect_bd_net -net p1_o_bit0_ioreq1_Dout
[
get_bd_pins extio8x4_axis_target_0/ioreq1_a
]
[
get_bd_pins p1_o_bit0_ioreq1/Dout
]
connect_bd_net -net p1_o_bit1_ioreq2_Dout
[
get_bd_pins extio8x4_axis_target_0/ioreq2_a
]
[
get_bd_pins p1_o_bit1_ioreq2/Dout
]
connect_bd_net -net p1_o_bit3_iodatata4_Dout
[
get_bd_pins extio8x4_axis_target_0/iodata4_i
]
[
get_bd_pins p1_o_bit3_iodatata4/Dout
]
connect_bd_net -net p1_z
[
get_bd_pins p1_tri_z
]
[
get_bd_pins axi_gpio_1/gpio2_io_i
]
connect_bd_net -net pmoda_i_1
[
get_bd_pins pmoda_tri_i
]
[
get_bd_pins pmoda_i_bit4/Din
]
[
get_bd_pins pmoda_i_bit7/Din
]
connect_bd_net -net pmoda_i_bit4_Dout
[
get_bd_pins swdio_tri_i
]
[
get_bd_pins pmoda_i_bit4/Dout
]
connect_bd_net -net pmoda_i_bit7_Dout
[
get_bd_pins swdclk_i
]
[
get_bd_pins pmoda_i_bit7/Dout
]
connect_bd_net -net pmoda_o_concat9_dout
[
get_bd_pins pmoda_tri_z
]
[
get_bd_pins pmoda_z_concat8/dout
]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn
[
get_bd_pins
ADPcontrol_0/ahb_hresetn
]
[
get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn
]
[
get_bd_pins axi_bram_ctrl_0/s_axi_aresetn
]
[
get_bd_pins
axi_gpio_0/s_axi_aresetn
]
[
get_bd_pins axi_gpio_1/s_axi_aresetn
]
[
get_bd_pins axi_stream_io_0/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_1/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_2/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_3/S_AXI_ARESETN
]
[
get_bd_pins axi_uartlite_0/s_axi_aresetn
]
[
get_bd_pins axi_uartlite_1/s_axi_aresetn
]
[
get_bd_pins axis_data_fifo_0/s_axis_aresetn
]
[
get_bd_pins
axis_data_fifo_1/s_axis_aresetn
]
[
get_bd_pins axis_data_fifo_2/s_axis_aresetn
]
[
get_bd_pins axis_data_fifo_3/s_axis_aresetn
]
[
get_bd_pins axis_data_fifo_4/s_axis_aresetn
]
[
get_bd_pins ft1248x1_to_axi_stream
_0/
a
resetn
]
[
get_bd_pins proc_sys_reset_0/interconnect_aresetn
]
[
get_bd_pins smartconnect_0/aresetn
]
connect_bd_net -net proc_sys_reset_0_interconnect_aresetn
[
get_bd_pins axi_gpio_0/s_axi_aresetn
]
[
get_bd_pins axi_gpio_1/s_axi_aresetn
]
[
get_bd_pins axi_stream_io_0/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_1/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_2/S_AXI_ARESETN
]
[
get_bd_pins axi_stream_io_3/S_AXI_ARESETN
]
[
get_bd_pins axi_uartlite_0/s_axi_aresetn
]
[
get_bd_pins axi_uartlite_1/s_axi_aresetn
]
[
get_bd_pins axis_data_fifo_0/s_axis_aresetn
]
[
get_bd_pins
extio8x4_axis_target
_0/resetn
]
[
get_bd_pins proc_sys_reset_0/interconnect_aresetn
]
[
get_bd_pins smartconnect_0/aresetn
]
connect_bd_net -net proc_sys_reset_0_peripheral_aresetn
[
get_bd_pins nrst
]
[
get_bd_pins proc_sys_reset_0/peripheral_aresetn
]
connect_bd_net -net swdio_o_1
[
get_bd_pins swdio_tri_o
]
[
get_bd_pins pmoda_o_concat8/In4
]
connect_bd_net -net swdio_z_1
[
get_bd_pins swdio_tri_z
]
[
get_bd_pins pmoda_z_concat8/In4
]
connect_bd_net -net xlconcat_0_dout
[
get_bd_pins pmoda_tri_o
]
[
get_bd_pins pmoda_o_concat8/dout
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0
[
get_bd_pins aclk
]
[
get_bd_pins ADPcontrol_0/ahb_hclk
]
[
get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk
]
[
get_bd_pins axi_bram_ctrl_0/s_axi_aclk
]
[
get_bd_pins axi_gpio_0/s_axi_aclk
]
[
get_bd_pins axi_gpio_1/s_axi_aclk
]
[
get_bd_pins axi_stream_io_0/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_1/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_2/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_3/S_AXI_ACLK
]
[
get_bd_pins axi_uartlite_0/s_axi_aclk
]
[
get_bd_pins axi_uartlite_1/s_axi_aclk
]
[
get_bd_pins axis_data_fifo_0/s_axis_aclk
]
[
get_bd_pins axis_data_fifo_1/s_axis_aclk
]
[
get_bd_pins axis_data_fifo_2/s_axis_aclk
]
[
get_bd_pins axis_data_fifo_3/s_axis_aclk
]
[
get_bd_pins axis_data_fifo_4/s_axis_aclk
]
[
get_bd_pins ft1248x1_to_axi_stream_0/aclk
]
[
get_bd_pins proc_sys_reset_0/slowest_sync_clk
]
[
get_bd_pins smartconnect_0/aclk
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0
[
get_bd_pins aclk
]
[
get_bd_pins axi_gpio_0/s_axi_aclk
]
[
get_bd_pins axi_gpio_1/s_axi_aclk
]
[
get_bd_pins axi_stream_io_0/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_1/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_2/S_AXI_ACLK
]
[
get_bd_pins axi_stream_io_3/S_AXI_ACLK
]
[
get_bd_pins axi_uartlite_0/s_axi_aclk
]
[
get_bd_pins axi_uartlite_1/s_axi_aclk
]
[
get_bd_pins axis_data_fifo_0/s_axis_aclk
]
[
get_bd_pins extio8x4_axis_target_0/clk
]
[
get_bd_pins proc_sys_reset_0/slowest_sync_clk
]
[
get_bd_pins smartconnect_0/aclk
]
connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0
[
get_bd_pins ext_reset_in
]
[
get_bd_pins proc_sys_reset_0/ext_reset_in
]
# Restore current instance
...
...
@@ -512,164 +378,472 @@ proc create_root_design { parentCell } {
# Create instance: zynq_ultra_ps_e_0, and set properties
set zynq_ultra_ps_e_0
[
create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0
]
set_property -dict
[
list
\
CONFIG.CAN0_BOARD_INTERFACE
{
custom
}
\
CONFIG.CAN1_BOARD_INTERFACE
{
custom
}
\
CONFIG.CSU_BOARD_INTERFACE
{
custom
}
\
CONFIG.DP_BOARD_INTERFACE
{
custom
}
\
CONFIG.GEM0_BOARD_INTERFACE
{
custom
}
\
CONFIG.GEM1_BOARD_INTERFACE
{
custom
}
\
CONFIG.GEM2_BOARD_INTERFACE
{
custom
}
\
CONFIG.GEM3_BOARD_INTERFACE
{
custom
}
\
CONFIG.GPIO_BOARD_INTERFACE
{
custom
}
\
CONFIG.IIC0_BOARD_INTERFACE
{
custom
}
\
CONFIG.IIC1_BOARD_INTERFACE
{
custom
}
\
CONFIG.NAND_BOARD_INTERFACE
{
custom
}
\
CONFIG.PCIE_BOARD_INTERFACE
{
custom
}
\
CONFIG.PJTAG_BOARD_INTERFACE
{
custom
}
\
CONFIG.PMU_BOARD_INTERFACE
{
custom
}
\
CONFIG.PSU_BANK_0_IO_STANDARD
{
LVCMOS18
}
\
CONFIG.PSU_BANK_1_IO_STANDARD
{
LVCMOS18
}
\
CONFIG.PSU_BANK_2_IO_STANDARD
{
LVCMOS18
}
\
CONFIG.PSU_BANK_3_IO_STANDARD
{
LVCMOS33
}
\
CONFIG.PSU_DDR_RAM_HIGHADDR
{
0x7FFFFFFF
}
\
CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET
{
0x00000002
}
\
CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET
{
0x80000000
}
\
CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN
{
0
}
\
CONFIG.PSU_IMPORT_BOARD_PRESET
{}
\
CONFIG.PSU_MIO_0_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_0_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_0_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_0_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_0_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_0_SLEW
{
fast
}
\
CONFIG.PSU_MIO_10_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_10_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_10_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_10_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_10_SLEW
{
fast
}
\
CONFIG.PSU_MIO_11_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_11_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_11_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_11_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_11_SLEW
{
fast
}
\
CONFIG.PSU_MIO_12_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_12_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_12_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_12_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_12_SLEW
{
fast
}
\
CONFIG.PSU_MIO_13_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_13_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_13_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_13_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_13_SLEW
{
fast
}
\
CONFIG.PSU_MIO_14_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_14_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_14_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_14_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_14_SLEW
{
fast
}
\
CONFIG.PSU_MIO_15_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_15_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_15_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_15_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_15_SLEW
{
fast
}
\
CONFIG.PSU_MIO_16_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_16_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_16_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_16_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_16_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_16_SLEW
{
fast
}
\
CONFIG.PSU_MIO_17_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_17_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_17_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_17_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_17_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_17_SLEW
{
fast
}
\
CONFIG.PSU_MIO_18_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_18_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_18_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_18_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_18_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_18_SLEW
{
fast
}
\
CONFIG.PSU_MIO_19_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_19_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_19_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_19_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_19_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_19_SLEW
{
fast
}
\
CONFIG.PSU_MIO_1_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_1_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_1_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_1_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_1_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_1_SLEW
{
fast
}
\
CONFIG.PSU_MIO_20_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_20_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_20_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_20_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_20_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_20_SLEW
{
fast
}
\
CONFIG.PSU_MIO_21_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_21_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_21_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_21_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_21_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_21_SLEW
{
fast
}
\
CONFIG.PSU_MIO_22_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_22_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_22_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_22_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_22_SLEW
{
fast
}
\
CONFIG.PSU_MIO_23_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_23_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_23_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_23_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_23_SLEW
{
fast
}
\
CONFIG.PSU_MIO_24_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_24_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_24_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_24_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_24_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_24_SLEW
{
fast
}
\
CONFIG.PSU_MIO_25_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_25_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_25_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_25_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_25_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_25_SLEW
{
fast
}
\
CONFIG.PSU_MIO_26_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_26_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_26_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_26_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_26_SLEW
{
fast
}
\
CONFIG.PSU_MIO_27_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_27_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_27_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_27_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_27_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_27_SLEW
{
fast
}
\
CONFIG.PSU_MIO_28_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_28_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_28_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_28_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_28_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_28_SLEW
{
fast
}
\
CONFIG.PSU_MIO_29_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_29_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_29_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_29_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_29_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_29_SLEW
{
fast
}
\
CONFIG.PSU_MIO_2_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_2_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_2_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_2_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_2_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_2_SLEW
{
fast
}
\
CONFIG.PSU_MIO_30_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_30_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_30_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_30_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_30_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_30_SLEW
{
fast
}
\
CONFIG.PSU_MIO_31_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_31_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_31_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_31_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_31_SLEW
{
fast
}
\
CONFIG.PSU_MIO_32_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_32_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_32_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_32_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_32_SLEW
{
fast
}
\
CONFIG.PSU_MIO_33_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_33_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_33_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_33_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_33_SLEW
{
fast
}
\
CONFIG.PSU_MIO_34_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_34_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_34_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_34_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_34_SLEW
{
fast
}
\
CONFIG.PSU_MIO_35_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_35_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_35_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_35_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_35_SLEW
{
fast
}
\
CONFIG.PSU_MIO_36_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_36_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_36_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_36_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_36_SLEW
{
fast
}
\
CONFIG.PSU_MIO_37_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_37_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_37_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_37_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_37_SLEW
{
fast
}
\
CONFIG.PSU_MIO_38_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_38_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_38_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_38_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_38_SLEW
{
fast
}
\
CONFIG.PSU_MIO_39_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_39_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_39_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_39_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_39_SLEW
{
fast
}
\
CONFIG.PSU_MIO_3_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_3_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_3_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_3_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_3_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_3_SLEW
{
fast
}
\
CONFIG.PSU_MIO_40_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_40_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_40_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_40_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_40_SLEW
{
fast
}
\
CONFIG.PSU_MIO_41_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_41_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_41_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_41_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_41_SLEW
{
fast
}
\
CONFIG.PSU_MIO_42_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_42_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_42_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_42_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_42_SLEW
{
fast
}
\
CONFIG.PSU_MIO_43_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_43_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_43_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_43_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_43_SLEW
{
fast
}
\
CONFIG.PSU_MIO_44_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_44_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_44_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_44_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_44_SLEW
{
fast
}
\
CONFIG.PSU_MIO_45_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_45_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_45_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_45_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_45_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_45_SLEW
{
fast
}
\
CONFIG.PSU_MIO_46_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_46_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_46_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_46_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_46_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_46_SLEW
{
fast
}
\
CONFIG.PSU_MIO_47_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_47_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_47_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_47_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_47_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_47_SLEW
{
fast
}
\
CONFIG.PSU_MIO_48_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_48_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_48_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_48_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_48_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_48_SLEW
{
fast
}
\
CONFIG.PSU_MIO_49_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_49_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_49_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_49_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_49_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_49_SLEW
{
fast
}
\
CONFIG.PSU_MIO_4_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_4_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_4_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_4_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_4_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_4_SLEW
{
fast
}
\
CONFIG.PSU_MIO_50_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_50_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_50_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_50_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_50_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_50_SLEW
{
fast
}
\
CONFIG.PSU_MIO_51_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_51_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_51_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_51_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_51_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_51_SLEW
{
fast
}
\
CONFIG.PSU_MIO_52_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_52_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_52_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_52_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_52_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_52_SLEW
{
fast
}
\
CONFIG.PSU_MIO_53_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_53_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_53_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_53_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_53_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_53_SLEW
{
fast
}
\
CONFIG.PSU_MIO_54_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_54_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_54_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_54_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_54_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_54_SLEW
{
fast
}
\
CONFIG.PSU_MIO_55_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_55_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_55_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_55_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_55_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_55_SLEW
{
fast
}
\
CONFIG.PSU_MIO_56_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_56_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_56_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_56_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_56_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_56_SLEW
{
fast
}
\
CONFIG.PSU_MIO_57_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_57_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_57_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_57_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_57_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_57_SLEW
{
fast
}
\
CONFIG.PSU_MIO_58_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_58_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_58_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_58_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_58_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_58_SLEW
{
fast
}
\
CONFIG.PSU_MIO_59_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_59_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_59_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_59_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_59_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_59_SLEW
{
fast
}
\
CONFIG.PSU_MIO_5_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_5_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_5_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_5_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_5_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_5_SLEW
{
fast
}
\
CONFIG.PSU_MIO_60_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_60_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_60_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_60_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_60_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_60_SLEW
{
fast
}
\
CONFIG.PSU_MIO_61_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_61_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_61_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_61_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_61_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_61_SLEW
{
fast
}
\
CONFIG.PSU_MIO_62_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_62_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_62_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_62_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_62_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_62_SLEW
{
fast
}
\
CONFIG.PSU_MIO_63_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_63_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_63_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_63_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_63_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_63_SLEW
{
fast
}
\
CONFIG.PSU_MIO_64_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_64_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_64_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_64_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_64_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_64_SLEW
{
fast
}
\
CONFIG.PSU_MIO_65_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_65_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_65_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_65_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_65_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_65_SLEW
{
fast
}
\
CONFIG.PSU_MIO_66_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_66_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_66_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_66_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_66_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_66_SLEW
{
fast
}
\
CONFIG.PSU_MIO_67_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_67_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_67_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_67_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_67_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_67_SLEW
{
fast
}
\
CONFIG.PSU_MIO_68_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_68_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_68_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_68_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_68_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_68_SLEW
{
fast
}
\
CONFIG.PSU_MIO_69_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_69_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_69_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_69_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_69_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_69_SLEW
{
fast
}
\
CONFIG.PSU_MIO_6_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_6_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_6_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_6_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_6_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_6_SLEW
{
fast
}
\
CONFIG.PSU_MIO_70_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_70_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_70_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_70_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_70_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_70_SLEW
{
fast
}
\
CONFIG.PSU_MIO_71_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_71_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_71_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_71_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_71_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_71_SLEW
{
fast
}
\
CONFIG.PSU_MIO_72_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_72_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_72_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_72_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_72_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_72_SLEW
{
fast
}
\
CONFIG.PSU_MIO_73_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_73_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_73_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_73_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_73_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_73_SLEW
{
fast
}
\
CONFIG.PSU_MIO_74_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_74_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_74_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_74_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_74_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_74_SLEW
{
fast
}
\
CONFIG.PSU_MIO_75_DIRECTION
{
in
}
\
CONFIG.PSU_MIO_75_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_75_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_75_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_75_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_75_SLEW
{
fast
}
\
CONFIG.PSU_MIO_76_DIRECTION
{
out
}
\
CONFIG.PSU_MIO_76_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_76_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_76_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_76_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_76_SLEW
{
fast
}
\
CONFIG.PSU_MIO_77_DIRECTION
{
inout
}
\
CONFIG.PSU_MIO_77_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_77_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_77_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_77_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_77_SLEW
{
fast
}
\
CONFIG.PSU_MIO_7_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_7_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_7_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_7_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_7_SLEW
{
fast
}
\
CONFIG.PSU_MIO_8_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_8_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_8_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_8_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_8_SLEW
{
fast
}
\
CONFIG.PSU_MIO_9_DRIVE_STRENGTH
{
12
}
\
CONFIG.PSU_MIO_9_INPUT_TYPE
{
cmos
}
\
CONFIG.PSU_MIO_9_POLARITY
{
Default
}
\
CONFIG.PSU_MIO_9_PULLUPDOWN
{
pullup
}
\
CONFIG.PSU_MIO_9_SLEW
{
fast
}
\
CONFIG.PSU_MIO_TREE_PERIPHERALS
{
Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad
\
SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN
\
1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD
\
...
...
@@ -677,9 +851,30 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO
\
3
}
\
CONFIG.PSU_MIO_TREE_SIGNALS
{
sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out
[
0
]
#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \
CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {8} \
CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
CONFIG.PSU_SMC_CYCLE_T0 {NA} \
CONFIG.PSU_SMC_CYCLE_T1 {NA} \
CONFIG.PSU_SMC_CYCLE_T2 {NA} \
CONFIG.PSU_SMC_CYCLE_T3 {NA} \
CONFIG.PSU_SMC_CYCLE_T4 {NA} \
CONFIG.PSU_SMC_CYCLE_T5 {NA} \
CONFIG.PSU_SMC_CYCLE_T6 {NA} \
CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
CONFIG.PSU_VALUE_SILVERSION {3} \
CONFIG.PSU__ACPU0__POWER__ON {1} \
CONFIG.PSU__ACPU1__POWER__ON {1} \
CONFIG.PSU__ACPU2__POWER__ON {1} \
CONFIG.PSU__ACPU3__POWER__ON {1} \
CONFIG.PSU__ACTUAL__IP {1} \
CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
CONFIG.PSU__AFI0_COHERENCY {0} \
CONFIG.PSU__AFI1_COHERENCY {0} \
CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \
CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
...
...
@@ -687,16 +882,52 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
CONFIG.PSU__CRF_APB__ACPU__FRAC_ENABLED {0} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \
CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \
CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \
CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \
CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
...
...
@@ -715,21 +946,25 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \
CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \
CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \
CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
...
...
@@ -740,6 +975,12 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \
CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \
CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
...
...
@@ -758,6 +999,7 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
...
...
@@ -765,12 +1007,21 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \
CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
...
...
@@ -780,17 +1031,36 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \
CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \
CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \
CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \
CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
...
...
@@ -799,7 +1069,9 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
...
...
@@ -812,6 +1084,7 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
...
...
@@ -827,8 +1100,15 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \
CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
...
...
@@ -838,12 +1118,21 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \
CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
...
...
@@ -852,20 +1141,30 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {27.138} \
CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {214} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {214} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \
CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {RPLL} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
...
...
@@ -885,15 +1184,48 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \
CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {0} \
CONFIG.PSU__CSU_COHERENCY {0} \
CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \
CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \
CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
CONFIG.PSU__DDRC__AL {0} \
CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
...
...
@@ -908,6 +1240,7 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
...
...
@@ -934,9 +1267,16 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
CONFIG.PSU__DDRC__ECC {Disabled} \
CONFIG.PSU__DDRC__ECC_SCRUB {0} \
CONFIG.PSU__DDRC__ENABLE {1} \
CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \
CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
CONFIG.PSU__DDRC__EN_2ND_CLK {0} \
CONFIG.PSU__DDRC__FGRM {1X} \
CONFIG.PSU__DDRC__FREQ_MHZ {1} \
CONFIG.PSU__DDRC__LPDDR3_DUALRANK_SDP {0} \
CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
CONFIG.PSU__DDRC__LP_ASR {manual normal} \
...
...
@@ -944,6 +1284,10 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
CONFIG.PSU__DDRC__PLL_BYPASS {0} \
CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \
CONFIG.PSU__DDRC__RANK_ADDR_COUNT {0} \
CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \
CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
...
...
@@ -958,9 +1302,32 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__DDRC__T_RCD {15} \
CONFIG.PSU__DDRC__T_RP {15} \
CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \
CONFIG.PSU__DDRC__VREF {1} \
CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
CONFIG.PSU__DDR_QOS_ENABLE {0} \
CONFIG.PSU__DDR_QOS_FIX_HP0_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP0_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP1_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP1_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP2_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP2_WRQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP3_RDQOS {} \
CONFIG.PSU__DDR_QOS_FIX_HP3_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP0_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP0_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP1_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP1_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP2_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP2_WRQOS {} \
CONFIG.PSU__DDR_QOS_HP3_RDQOS {} \
CONFIG.PSU__DDR_QOS_HP3_WRQOS {} \
CONFIG.PSU__DDR_QOS_RD_HPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_RD_LPR_THRSHLD {} \
CONFIG.PSU__DDR_QOS_WR_THRSHLD {} \
CONFIG.PSU__DDR_SW_REFRESH_ENABLED {1} \
CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
CONFIG.PSU__DEVICE_TYPE {EV} \
CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
...
...
@@ -972,6 +1339,22 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
CONFIG.PSU__DP__REF_CLK_FREQ {27} \
CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \
CONFIG.PSU__ENET0__FIFO__ENABLE {0} \
CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET0__PTP__ENABLE {0} \
CONFIG.PSU__ENET0__TSU__ENABLE {0} \
CONFIG.PSU__ENET1__FIFO__ENABLE {0} \
CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET1__PTP__ENABLE {0} \
CONFIG.PSU__ENET1__TSU__ENABLE {0} \
CONFIG.PSU__ENET2__FIFO__ENABLE {0} \
CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \
CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__ENET2__PTP__ENABLE {0} \
CONFIG.PSU__ENET2__TSU__ENABLE {0} \
CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
...
...
@@ -979,21 +1362,76 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
CONFIG.PSU__ENET3__PTP__ENABLE {0} \
CONFIG.PSU__ENET3__TSU__ENABLE {0} \
CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \
CONFIG.PSU__EN_EMIO_TRACE {0} \
CONFIG.PSU__EP__IP {0} \
CONFIG.PSU__EXPAND__CORESIGHT {0} \
CONFIG.PSU__EXPAND__FPD_SLAVES {0} \
CONFIG.PSU__EXPAND__GIC {0} \
CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \
CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \
CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__FPGA_PL0_ENABLE {1} \
CONFIG.PSU__FPGA_PL1_ENABLE {0} \
CONFIG.PSU__FPGA_PL2_ENABLE {0} \
CONFIG.PSU__FPGA_PL3_ENABLE {0} \
CONFIG.PSU__FP__POWER__ON {1} \
CONFIG.PSU__FTM__CTI_IN_0 {0} \
CONFIG.PSU__FTM__CTI_IN_1 {0} \
CONFIG.PSU__FTM__CTI_IN_2 {0} \
CONFIG.PSU__FTM__CTI_IN_3 {0} \
CONFIG.PSU__FTM__CTI_OUT_0 {0} \
CONFIG.PSU__FTM__CTI_OUT_1 {0} \
CONFIG.PSU__FTM__CTI_OUT_2 {0} \
CONFIG.PSU__FTM__CTI_OUT_3 {0} \
CONFIG.PSU__FTM__GPI {0} \
CONFIG.PSU__FTM__GPO {0} \
CONFIG.PSU__GEM0_COHERENCY {0} \
CONFIG.PSU__GEM0_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__GEM1_COHERENCY {0} \
CONFIG.PSU__GEM1_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__GEM2_COHERENCY {0} \
CONFIG.PSU__GEM2_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__GEM3_COHERENCY {0} \
CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__GEM__TSU__ENABLE {0} \
CONFIG.PSU__GEN_IPI_0__MASTER {APU} \
CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \
CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \
CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \
CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \
CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \
CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO_WIDTH {1} \
CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__GPIO_EMIO__WIDTH {[94:0]} \
CONFIG.PSU__GPU_PP0__POWER__ON {1} \
CONFIG.PSU__GPU_PP1__POWER__ON {1} \
CONFIG.PSU__GT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__GT__LINK_SPEED {HBR} \
CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
CONFIG.PSU__HPM0_FPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM0_FPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__HPM0_LPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM0_LPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__HPM1_FPD__NUM_READ_THREADS {4} \
CONFIG.PSU__HPM1_FPD__NUM_WRITE_THREADS {4} \
CONFIG.PSU__I2C0_LOOP_I2C1__ENABLE {0} \
CONFIG.PSU__I2C0__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__I2C1__GRP_INT__ENABLE {0} \
CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
...
...
@@ -1011,15 +1449,266 @@ SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__IRQ_P2F_ADMA_CHAN__INT {0} \
CONFIG.PSU__IRQ_P2F_AIB_AXI__INT {0} \
CONFIG.PSU__IRQ_P2F_AMS__INT {0} \
CONFIG.PSU__IRQ_P2F_APM_FPD__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_COMM__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_CPUMNT__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_CTI__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_EXTERR__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_L2ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_PMU__INT {0} \
CONFIG.PSU__IRQ_P2F_APU_REGS__INT {0} \
CONFIG.PSU__IRQ_P2F_ATB_LPD__INT {0} \
CONFIG.PSU__IRQ_P2F_CAN0__INT {0} \
CONFIG.PSU__IRQ_P2F_CAN1__INT {0} \
CONFIG.PSU__IRQ_P2F_CLKMON__INT {0} \
CONFIG.PSU__IRQ_P2F_CSUPMU_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_CSU_DMA__INT {0} \
CONFIG.PSU__IRQ_P2F_CSU__INT {0} \
CONFIG.PSU__IRQ_P2F_DDR_SS__INT {0} \
CONFIG.PSU__IRQ_P2F_DPDMA__INT {0} \
CONFIG.PSU__IRQ_P2F_DPORT__INT {0} \
CONFIG.PSU__IRQ_P2F_EFUSE__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT0_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT0__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT1_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT1__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT2_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT2__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT3_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_ENT3__INT {0} \
CONFIG.PSU__IRQ_P2F_FPD_APB__INT {0} \
CONFIG.PSU__IRQ_P2F_FPD_ATB_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_FP_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_GDMA_CHAN__INT {0} \
CONFIG.PSU__IRQ_P2F_GPIO__INT {0} \
CONFIG.PSU__IRQ_P2F_GPU__INT {0} \
CONFIG.PSU__IRQ_P2F_I2C0__INT {0} \
CONFIG.PSU__IRQ_P2F_I2C1__INT {0} \
CONFIG.PSU__IRQ_P2F_LPD_APB__INT {0} \
CONFIG.PSU__IRQ_P2F_LPD_APM__INT {0} \
CONFIG.PSU__IRQ_P2F_LP_WDT__INT {0} \
CONFIG.PSU__IRQ_P2F_NAND__INT {0} \
CONFIG.PSU__IRQ_P2F_OCM_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_DMA__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_LEGACY__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_MSC__INT {0} \
CONFIG.PSU__IRQ_P2F_PCIE_MSI__INT {0} \
CONFIG.PSU__IRQ_P2F_PL_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_QSPI__INT {0} \
CONFIG.PSU__IRQ_P2F_R5_CORE0_ECC_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_R5_CORE1_ECC_ERR__INT {0} \
CONFIG.PSU__IRQ_P2F_RPU_IPI__INT {0} \
CONFIG.PSU__IRQ_P2F_RPU_PERMON__INT {0} \
CONFIG.PSU__IRQ_P2F_RTC_ALARM__INT {0} \
CONFIG.PSU__IRQ_P2F_RTC_SECONDS__INT {0} \
CONFIG.PSU__IRQ_P2F_SATA__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO0_WAKE__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO0__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO1_WAKE__INT {0} \
CONFIG.PSU__IRQ_P2F_SDIO1__INT {0} \
CONFIG.PSU__IRQ_P2F_SPI0__INT {0} \
CONFIG.PSU__IRQ_P2F_SPI1__INT {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC0__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC1__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC2__INT2 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT0 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT1 {0} \
CONFIG.PSU__IRQ_P2F_TTC3__INT2 {0} \
CONFIG.PSU__IRQ_P2F_UART0__INT {0} \
CONFIG.PSU__IRQ_P2F_UART1__INT {0} \
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT0 {0} \
CONFIG.PSU__IRQ_P2F_USB3_ENDPOINT__INT1 {0} \
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT0 {0} \
CONFIG.PSU__IRQ_P2F_USB3_OTG__INT1 {0} \
CONFIG.PSU__IRQ_P2F_USB3_PMU_WAKEUP__INT {0} \
CONFIG.PSU__IRQ_P2F_XMPU_FPD__INT {0} \
CONFIG.PSU__IRQ_P2F_XMPU_LPD__INT {0} \
CONFIG.PSU__IRQ_P2F__INTF_FPD_SMMU__INT {0} \
CONFIG.PSU__IRQ_P2F__INTF_PPD_CCI__INT {0} \
CONFIG.PSU__L2_BANK0__POWER__ON {1} \
CONFIG.PSU__LPDMA0_COHERENCY {0} \
CONFIG.PSU__LPDMA1_COHERENCY {0} \
CONFIG.PSU__LPDMA2_COHERENCY {0} \
CONFIG.PSU__LPDMA3_COHERENCY {0} \
CONFIG.PSU__LPDMA4_COHERENCY {0} \
CONFIG.PSU__LPDMA5_COHERENCY {0} \
CONFIG.PSU__LPDMA6_COHERENCY {0} \
CONFIG.PSU__LPDMA7_COHERENCY {0} \
CONFIG.PSU__LPD_SLCR__CSUPMU_WDT_CLK_SEL__SELECT {APB} \
CONFIG.PSU__LPD_SLCR__CSUPMU__ACT_FREQMHZ {100} \
CONFIG.PSU__LPD_SLCR__CSUPMU__FREQMHZ {100} \
CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
CONFIG.PSU__M_AXI_GP0_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__M_AXI_GP1_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__M_AXI_GP2_SUPPORTS_NARROW_BURST {1} \
CONFIG.PSU__NAND_COHERENCY {0} \
CONFIG.PSU__NAND_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__NAND__CHIP_ENABLE__ENABLE {0} \
CONFIG.PSU__NAND__DATA_STROBE__ENABLE {0} \
CONFIG.PSU__NAND__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__NAND__READY0_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY1_BUSY__ENABLE {0} \
CONFIG.PSU__NAND__READY_BUSY__ENABLE {0} \
CONFIG.PSU__NUM_FABRIC_RESETS {1} \
CONFIG.PSU__OCM_BANK0__POWER__ON {1} \
CONFIG.PSU__OCM_BANK1__POWER__ON {1} \
CONFIG.PSU__OCM_BANK2__POWER__ON {1} \
CONFIG.PSU__OCM_BANK3__POWER__ON {1} \
CONFIG.PSU__OVERRIDE_HPX_QOS {0} \
CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
CONFIG.PSU__PCIE__ACS_VIOLAION {0} \
CONFIG.PSU__PCIE__ACS_VIOLATION {0} \
CONFIG.PSU__PCIE__AER_CAPABILITY {0} \
CONFIG.PSU__PCIE__ATOMICOP_EGRESS_BLOCKED {0} \
CONFIG.PSU__PCIE__BAR0_64BIT {0} \
CONFIG.PSU__PCIE__BAR0_ENABLE {0} \
CONFIG.PSU__PCIE__BAR0_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR0_VAL {} \
CONFIG.PSU__PCIE__BAR1_64BIT {0} \
CONFIG.PSU__PCIE__BAR1_ENABLE {0} \
CONFIG.PSU__PCIE__BAR1_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR1_VAL {} \
CONFIG.PSU__PCIE__BAR2_64BIT {0} \
CONFIG.PSU__PCIE__BAR2_ENABLE {0} \
CONFIG.PSU__PCIE__BAR2_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR2_VAL {} \
CONFIG.PSU__PCIE__BAR3_64BIT {0} \
CONFIG.PSU__PCIE__BAR3_ENABLE {0} \
CONFIG.PSU__PCIE__BAR3_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR3_VAL {} \
CONFIG.PSU__PCIE__BAR4_64BIT {0} \
CONFIG.PSU__PCIE__BAR4_ENABLE {0} \
CONFIG.PSU__PCIE__BAR4_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR4_VAL {} \
CONFIG.PSU__PCIE__BAR5_64BIT {0} \
CONFIG.PSU__PCIE__BAR5_ENABLE {0} \
CONFIG.PSU__PCIE__BAR5_PREFETCHABLE {0} \
CONFIG.PSU__PCIE__BAR5_VAL {} \
CONFIG.PSU__PCIE__CLASS_CODE_BASE {} \
CONFIG.PSU__PCIE__CLASS_CODE_INTERFACE {} \
CONFIG.PSU__PCIE__CLASS_CODE_SUB {} \
CONFIG.PSU__PCIE__CLASS_CODE_VALUE {} \
CONFIG.PSU__PCIE__COMPLETER_ABORT {0} \
CONFIG.PSU__PCIE__COMPLTION_TIMEOUT {0} \
CONFIG.PSU__PCIE__CORRECTABLE_INT_ERR {0} \
CONFIG.PSU__PCIE__CRS_SW_VISIBILITY {0} \
CONFIG.PSU__PCIE__DEVICE_ID {} \
CONFIG.PSU__PCIE__ECRC_CHECK {0} \
CONFIG.PSU__PCIE__ECRC_ERR {0} \
CONFIG.PSU__PCIE__ECRC_GEN {0} \
CONFIG.PSU__PCIE__EROM_ENABLE {0} \
CONFIG.PSU__PCIE__EROM_VAL {} \
CONFIG.PSU__PCIE__FLOW_CONTROL_ERR {0} \
CONFIG.PSU__PCIE__FLOW_CONTROL_PROTOCOL_ERR {0} \
CONFIG.PSU__PCIE__HEADER_LOG_OVERFLOW {0} \
CONFIG.PSU__PCIE__INTX_GENERATION {0} \
CONFIG.PSU__PCIE__LANE0__ENABLE {0} \
CONFIG.PSU__PCIE__LANE1__ENABLE {0} \
CONFIG.PSU__PCIE__LANE2__ENABLE {0} \
CONFIG.PSU__PCIE__LANE3__ENABLE {0} \
CONFIG.PSU__PCIE__MC_BLOCKED_TLP {0} \
CONFIG.PSU__PCIE__MSIX_BAR_INDICATOR {} \
CONFIG.PSU__PCIE__MSIX_CAPABILITY {0} \
CONFIG.PSU__PCIE__MSIX_PBA_BAR_INDICATOR {} \
CONFIG.PSU__PCIE__MSIX_PBA_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_OFFSET {0} \
CONFIG.PSU__PCIE__MSIX_TABLE_SIZE {0} \
CONFIG.PSU__PCIE__MSI_64BIT_ADDR_CAPABLE {0} \
CONFIG.PSU__PCIE__MSI_CAPABILITY {0} \
CONFIG.PSU__PCIE__MULTIHEADER {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PCIE__PERIPHERAL__ENDPOINT_ENABLE {1} \
CONFIG.PSU__PCIE__PERIPHERAL__ROOTPORT_ENABLE {0} \
CONFIG.PSU__PCIE__PERM_ROOT_ERR_UPDATE {0} \
CONFIG.PSU__PCIE__RECEIVER_ERR {0} \
CONFIG.PSU__PCIE__RECEIVER_OVERFLOW {0} \
CONFIG.PSU__PCIE__RESET__POLARITY {Active Low} \
CONFIG.PSU__PCIE__REVISION_ID {} \
CONFIG.PSU__PCIE__SUBSYSTEM_ID {} \
CONFIG.PSU__PCIE__SUBSYSTEM_VENDOR_ID {} \
CONFIG.PSU__PCIE__SURPRISE_DOWN {0} \
CONFIG.PSU__PCIE__TLP_PREFIX_BLOCKED {0} \
CONFIG.PSU__PCIE__UNCORRECTABL_INT_ERR {0} \
CONFIG.PSU__PCIE__VENDOR_ID {} \
CONFIG.PSU__PJTAG__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PL_CLK0_BUF {TRUE} \
CONFIG.PSU__PL_CLK1_BUF {FALSE} \
CONFIG.PSU__PL_CLK2_BUF {FALSE} \
CONFIG.PSU__PL_CLK3_BUF {FALSE} \
CONFIG.PSU__PL__POWER__ON {1} \
CONFIG.PSU__PMU_COHERENCY {0} \
CONFIG.PSU__PMU__AIBACK__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPI__ENABLE {0} \
CONFIG.PSU__PMU__EMIO_GPO__ENABLE {0} \
CONFIG.PSU__PMU__GPI0__ENABLE {0} \
CONFIG.PSU__PMU__GPI1__ENABLE {0} \
CONFIG.PSU__PMU__GPI2__ENABLE {0} \
CONFIG.PSU__PMU__GPI3__ENABLE {0} \
CONFIG.PSU__PMU__GPI4__ENABLE {0} \
CONFIG.PSU__PMU__GPI5__ENABLE {0} \
CONFIG.PSU__PMU__GPO0__ENABLE {0} \
CONFIG.PSU__PMU__GPO1__ENABLE {0} \
CONFIG.PSU__PMU__GPO2__ENABLE {0} \
CONFIG.PSU__PMU__GPO3__ENABLE {0} \
CONFIG.PSU__PMU__GPO4__ENABLE {0} \
CONFIG.PSU__PMU__GPO5__ENABLE {0} \
CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__PMU__PLERROR__ENABLE {0} \
CONFIG.PSU__PRESET_APPLIED {1} \
CONFIG.PSU__PROTECTION__DDR_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__DEBUG {0} \
CONFIG.PSU__PROTECTION__ENABLE {0} \
CONFIG.PSU__PROTECTION__FPD_SEGMENTS {SA:0xFD1A0000; SIZE:1280; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware| SA:0xFD000000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD010000; SIZE:64;\
UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
SA:0xFD020000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware| SA:0xFD030000; SIZE:64; UNIT:KB; RegionTZ:Secure;\
WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD040000; SIZE:64;\
UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
SA:0xFD050000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware| SA:0xFD610000; SIZE:512; UNIT:KB; RegionTZ:Secure;\
WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFD5D0000; SIZE:64;\
UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU\
Firmware|SA:0xFD1A0000 ; SIZE:1280; UNIT:KB; RegionTZ:Secure ;\
WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
CONFIG.PSU__PROTECTION__LOCK_UNUSED_SEGMENTS {0} \
CONFIG.PSU__PROTECTION__LPD_SEGMENTS {SA:0xFF980000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware| SA:0xFF5E0000; SIZE:2560; UNIT:KB; RegionTZ:Secure;\
WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFCC0000; SIZE:64;\
UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
SA:0xFF180000; SIZE:768; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware| SA:0xFF410000; SIZE:640; UNIT:KB; RegionTZ:Secure;\
WrAllowed:Read/Write; subsystemId:PMU Firmware| SA:0xFFA70000; SIZE:64;\
UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write; subsystemId:PMU Firmware|\
SA:0xFF9A0000; SIZE:64; UNIT:KB; RegionTZ:Secure; WrAllowed:Read/Write;\
subsystemId:PMU Firmware|SA:0xFF5E0000 ; SIZE:2560; UNIT:KB; RegionTZ:Secure ;\
WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFFCC0000 ; SIZE:64;\
UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure\
Subsystem|SA:0xFF180000 ; SIZE:768; UNIT:KB; RegionTZ:Secure ;\
WrAllowed:Read/Write; subsystemId:Secure Subsystem|SA:0xFF9A0000 ; SIZE:64;\
UNIT:KB; RegionTZ:Secure ; WrAllowed:Read/Write; subsystemId:Secure Subsystem}\
CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
CONFIG.PSU__PROTECTION__MASTERS_TZ {GEM0:NonSecure|SD1:NonSecure|GEM2:NonSecure|GEM1:NonSecure|GEM3:NonSecure|PCIe:NonSecure|DP:NonSecure|NAND:NonSecure|GPU:NonSecure|USB1:NonSecure|USB0:NonSecure|LDMA:NonSecure|FDMA:NonSecure|QSPI:NonSecure|SD0:NonSecure}\
CONFIG.PSU__PROTECTION__OCM_SEGMENTS {NONE} \
CONFIG.PSU__PROTECTION__PRESUBSYSTEMS {NONE} \
CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
CONFIG.PSU__PROTECTION__SUBSYSTEMS {PMU Firmware:PMU|Secure Subsystem:} \
CONFIG.PSU__PSS_ALT_REF_CLK__ENABLE {0} \
CONFIG.PSU__PSS_ALT_REF_CLK__FREQMHZ {33.333} \
CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
CONFIG.PSU__QSPI_COHERENCY {0} \
CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
...
...
@@ -1029,12 +1718,29 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
CONFIG.PSU__REPORT__DBGLOG {0} \
CONFIG.PSU__RPU_COHERENCY {0} \
CONFIG.PSU__RPU__POWER__ON {1} \
CONFIG.PSU__SATA__LANE0__ENABLE {0} \
CONFIG.PSU__SATA__LANE1__ENABLE {1} \
CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
CONFIG.PSU__SAXIGP0__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP1__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP2__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP3__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP4__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP5__DATA_WIDTH {128} \
CONFIG.PSU__SAXIGP6__DATA_WIDTH {128} \
CONFIG.PSU__SD0_COHERENCY {0} \
CONFIG.PSU__SD0_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD0__GRP_CD__ENABLE {0} \
CONFIG.PSU__SD0__GRP_POW__ENABLE {0} \
CONFIG.PSU__SD0__GRP_WP__ENABLE {0} \
CONFIG.PSU__SD0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SD0__RESET__ENABLE {0} \
CONFIG.PSU__SD1_COHERENCY {0} \
CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
...
...
@@ -1046,25 +1752,50 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
CONFIG.PSU__SD1__RESET__ENABLE {0} \
CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
CONFIG.PSU__SPI0_LOOP_SPI1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI0__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI0__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS0__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS1__ENABLE {0} \
CONFIG.PSU__SPI1__GRP_SS2__ENABLE {0} \
CONFIG.PSU__SPI1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT0__PERIPHERAL__IO {NA} \
CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__SWDT1__PERIPHERAL__IO {NA} \
CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
CONFIG.PSU__TCM0A__POWER__ON {1} \
CONFIG.PSU__TCM0B__POWER__ON {1} \
CONFIG.PSU__TCM1A__POWER__ON {1} \
CONFIG.PSU__TCM1B__POWER__ON {1} \
CONFIG.PSU__TESTSCAN__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__TRACE_PIPELINE_WIDTH {8} \
CONFIG.PSU__TRACE__INTERNAL_WIDTH {32} \
CONFIG.PSU__TRACE__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__TRISTATE__INVERTED {1} \
CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC0__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC1__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC2__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__TTC3__PERIPHERAL__IO {NA} \
CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
CONFIG.PSU__UART0_LOOP_UART1__ENABLE {0} \
CONFIG.PSU__UART0__BAUD_RATE {115200} \
CONFIG.PSU__UART0__MODEM__ENABLE {0} \
CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
...
...
@@ -1079,17 +1810,87 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
CONFIG.PSU__USB0__RESET__ENABLE {0} \
CONFIG.PSU__USB1_COHERENCY {0} \
CONFIG.PSU__USB1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB1__RESET__ENABLE {0} \
CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB2_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
CONFIG.PSU__USB3_1__EMIO__ENABLE {0} \
CONFIG.PSU__USB3_1__PERIPHERAL__ENABLE {0} \
CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP0 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP1 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP2 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP3 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP4 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP5 {0} \
CONFIG.PSU__USE_DIFF_RW_CLK_GP6 {0} \
CONFIG.PSU__USE__ADMA {0} \
CONFIG.PSU__USE__APU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__AUDIO {0} \
CONFIG.PSU__USE__CLK {0} \
CONFIG.PSU__USE__CLK0 {0} \
CONFIG.PSU__USE__CLK1 {0} \
CONFIG.PSU__USE__CLK2 {0} \
CONFIG.PSU__USE__CLK3 {0} \
CONFIG.PSU__USE__CROSS_TRIGGER {0} \
CONFIG.PSU__USE__DDR_INTF_REQUESTED {0} \
CONFIG.PSU__USE__DEBUG__TEST {0} \
CONFIG.PSU__USE__EVENT_RPU {0} \
CONFIG.PSU__USE__FABRIC__RST {1} \
CONFIG.PSU__USE__FTM {0} \
CONFIG.PSU__USE__GDMA {0} \
CONFIG.PSU__USE__IRQ {0} \
CONFIG.PSU__USE__IRQ0 {1} \
CONFIG.PSU__USE__IRQ1 {0} \
CONFIG.PSU__USE__M_AXI_GP0 {0} \
CONFIG.PSU__USE__M_AXI_GP1 {0} \
CONFIG.PSU__USE__M_AXI_GP2 {1} \
CONFIG.PSU__USE__PROC_EVENT_BUS {0} \
CONFIG.PSU__USE__RPU_LEGACY_INTERRUPT {0} \
CONFIG.PSU__USE__RST0 {0} \
CONFIG.PSU__USE__RST1 {0} \
CONFIG.PSU__USE__RST2 {0} \
CONFIG.PSU__USE__RST3 {0} \
CONFIG.PSU__USE__RTC {0} \
CONFIG.PSU__USE__STM {0} \
CONFIG.PSU__USE__S_AXI_ACE {0} \
CONFIG.PSU__USE__S_AXI_ACP {0} \
CONFIG.PSU__USE__S_AXI_GP0 {0} \
CONFIG.PSU__USE__S_AXI_GP1 {0} \
CONFIG.PSU__USE__S_AXI_GP2 {0} \
CONFIG.PSU__USE__S_AXI_GP3 {0} \
CONFIG.PSU__USE__S_AXI_GP4 {0} \
CONFIG.PSU__USE__S_AXI_GP5 {0} \
CONFIG.PSU__USE__S_AXI_GP6 {0} \
CONFIG.PSU__USE__USB3_0_HUB {0} \
CONFIG.PSU__USE__USB3_1_HUB {0} \
CONFIG.PSU__USE__VIDEO {0} \
CONFIG.PSU__VIDEO_REF_CLK__ENABLE {0} \
CONFIG.PSU__VIDEO_REF_CLK__FREQMHZ {33.333} \
CONFIG.QSPI_BOARD_INTERFACE {custom} \
CONFIG.SATA_BOARD_INTERFACE {custom} \
CONFIG.SD0_BOARD_INTERFACE {custom} \
CONFIG.SD1_BOARD_INTERFACE {custom} \
CONFIG.SPI0_BOARD_INTERFACE {custom} \
CONFIG.SPI1_BOARD_INTERFACE {custom} \
CONFIG.SUBPRESET1 {Custom} \
CONFIG.SUBPRESET2 {Custom} \
CONFIG.SWDT0_BOARD_INTERFACE {custom} \
CONFIG.SWDT1_BOARD_INTERFACE {custom} \
CONFIG.TRACE_BOARD_INTERFACE {custom} \
CONFIG.TTC0_BOARD_INTERFACE {custom} \
CONFIG.TTC1_BOARD_INTERFACE {custom} \
CONFIG.TTC2_BOARD_INTERFACE {custom} \
CONFIG.TTC3_BOARD_INTERFACE {custom} \
CONFIG.UART0_BOARD_INTERFACE {custom} \
CONFIG.UART1_BOARD_INTERFACE {custom} \
CONFIG.USB0_BOARD_INTERFACE {custom} \
CONFIG.USB1_BOARD_INTERFACE {custom} \
] $zynq_ultra_ps_e_0
# Create interface connections
...
...
@@ -1122,7 +1923,6 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg
]
-force
assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg
]
-force
assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space
[
get_bd_addr_spaces zynq_ultra_ps_e_0/Data
]
[
get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg
]
-force
assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space
[
get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb
]
[
get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0
]
-force
# Restore current instance
...
...
This diff is collapsed.
Click to expand it.
dwf1m12 authored