Skip to content
Snippets Groups Projects
Commit f64b582c authored by dam1n19's avatar dam1n19
Browse files

Further Restructured Repository to change directoyr hierarchy

parent fa7ecce0
No related branches found
No related tags found
1 merge request!1changed imem to rom to allow initial program loading, updated bootloader code...
Expand all Show whitespace changes
Inline Side-by-side
Showing
with 0 additions and 1493 deletions
system/makefile → makefile
+ 0
− 0
View file @ f64b582c
File moved
system/aes/aes128_tests/makefile deleted 100644 → 0
+ 0
− 262
View file @ fa7ecce0
#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from Arm Limited or its affiliates.
#
# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from Arm Limited or its affiliates.
#
# SVN Information
#
# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
#
# Revision : $Revision: 371321 $
#
# Release Information : Cortex-M System Design Kit-r1p1-00rel0
#-----------------------------------------------------------------------------
#
# Cortex-M System Design Kit software compilation make file
#
#-----------------------------------------------------------------------------
#
# Configurations
#
# Choose the core instantiated, can be
# - CORTEX_M0
# - CORTEX_M0PLUS
CPU_PRODUCT = CORTEX_M0
# Shared software directory
SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
else
DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
endif
# Program file
TESTNAME = aes128_tests
# Endian Option
COMPILE_BIGEND = 0
# Configuration
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
USER_DEFINE = -DCORTEX_M0PLUS
else
USER_DEFINE = -DCORTEX_M0
endif
DEPS_LIST = makefile
# Tool chain : ds5 / gcc / keil
TOOL_CHAIN = ds5
ifeq ($(TOOL_CHAIN),ds5)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = --cpu Cortex-M0plus
else
CPU_TYPE = --cpu Cortex-M0
endif
endif
ifeq ($(TOOL_CHAIN),gcc)
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
CPU_TYPE = -mcpu=cortex-m0plus
else
CPU_TYPE = -mcpu=cortex-m0
endif
endif
# Startup code directory for DS-5
ifeq ($(TOOL_CHAIN),ds5)
STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
endif
# Startup code directory for gcc
ifeq ($(TOOL_CHAIN),gcc)
STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
endif
ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
STARTUP_FILE = startup_CMSDK_CM0plus
SYSTEM_FILE = system_CMSDK_CM0plus
else
STARTUP_FILE = startup_CMSDK_CM0
SYSTEM_FILE = system_CMSDK_CM0
endif
# ---------------------------------------------------------------------------------------
# DS-5 options
# MicroLIB option
COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
#ARM_ASM_OPTIONS = -g
#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
ARM_CC_OPTIONS += --bigend
ARM_ASM_OPTIONS += --bigend
ARM_LINK_OPTIONS += --be8
endif
ifeq ($(COMPILE_MICROLIB),1)
# MicroLIB
ARM_CC_OPTIONS += --library_type=microlib
ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
ARM_LINK_OPTIONS += --library_type=microlib
endif
ifeq ($(COMPILE_SMALLMUL),1)
# In Cortex-M0, small multiply takes 32 cycles
ARM_CC_OPTIONS += --multiply_latency=32
endif
# ---------------------------------------------------------------------------------------
# gcc options
GNG_CC = arm-none-eabi-gcc
GNU_OBJDUMP = arm-none-eabi-objdump
GNU_OBJCOPY = arm-none-eabi-objcopy
LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
ifeq ($(COMPILE_BIGEND),1)
# Big Endian
GNU_CC_FLAGS += -mbig-endian
endif
# ---------------------------------------------------------------------------------------
all: all_$(TOOL_CHAIN)
# ---------------------------------------------------------------------------------------
# DS-5
all_ds5 : $(TESTNAME).hex $(TESTNAME).lst $(TESTNAME).bin
$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
dma_pl230_driver.o : dma_pl230_driver.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
$(TESTNAME).ELF : $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
$(TESTNAME).hex : $(TESTNAME).ELF
fromelf --vhx --8x1 $< --output $@
$(TESTNAME).lst : $(TESTNAME).ELF
fromelf -c -d -e -s -z -v $< --output $@
$(TESTNAME).bin : $(TESTNAME).ELF
fromelf --bin $< --output $@
# ---------------------------------------------------------------------------------------
# gcc
all_gcc:
$(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
$(TESTNAME).c \
$(SOFTWARE_DIR)/common/retarget/retarget.c \
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-I $(SOFTWARE_DIR)/common/retarget \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \
$(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
# Generate disassembly code
$(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
# Generate binary file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
# Generate hex file
$(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
# Note:
# If the version of object copy you are using does not support verilog hex file output,
# you can generate the hex file from binary file using the following command
# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Keil MDK
all_keil:
@echo "Please compile your project code and press ENTER when ready"
@read dummy
# ---------------------------------------------------------------------------------------
# Binary
all_bin: $(TESTNAME).bin
# Generate hex file from binary
od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
# ---------------------------------------------------------------------------------------
# Clean
clean :
@rm -rf *.o
@if [ -e $(TESTNAME).hex ] ; then \
rm -rf $(TESTNAME).hex ; \
fi
@if [ -e $(TESTNAME).lst ] ; then \
rm -rf $(TESTNAME).lst ; \
fi
@if [ -e $(TESTNAME).ELF ] ; then \
rm -rf $(TESTNAME).ELF ; \
fi
@if [ -e $(TESTNAME).bin ] ; then \
rm -rf $(TESTNAME).bin ; \
fi
@rm -rf *.crf
@rm -rf *.plg
@rm -rf *.tra
@rm -rf *.htm
@rm -rf *.map
@rm -rf *.dep
@rm -rf *.d
@rm -rf *.lnp
@rm -rf *.bak
@rm -rf *.lst
@rm -rf *.axf
@rm -rf *.sct
@rm -rf *.__i
@rm -rf *._ia
system/aes/src/nanosoc_acc_wrapper.v deleted 100644 → 0
+ 0
− 75
View file @ fa7ecce0
//-----------------------------------------------------------------------------
// SoC Labs Basic Example Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_acc_wrapper #(
parameter AHBADDRWIDTH=16,
parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=128,
parameter CFGNUMIRQ=4
) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSELS,
input wire [AHBADDRWIDTH-1:0] HADDRS,
input wire [1:0] HTRANSS,
input wire [2:0] HSIZES,
input wire [3:0] HPROTS,
input wire HWRITES,
input wire HREADYS,
input wire [31:0] HWDATAS,
output wire HREADYOUTS,
output wire HRESPS,
output wire [31:0] HRDATAS,
// Input Data Request Signal to DMAC
output wire exp_drq_ip_o,
input wire exp_dlast_ip_i,
// Output Data Request Signal to DMAC
output wire exp_drq_op_o,
input wire exp_dlast_op_i,
// Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o
);
soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSELS),
.ahb_haddr16 (HADDRS[15:0]),
.ahb_htrans (HTRANSS),
.ahb_hwrite (HWRITES),
.ahb_hsize (HSIZES),
.ahb_hprot (HPROTS),
.ahb_hwdata (HWDATAS),
.ahb_hready (HREADYS),
.ahb_hrdata (HRDATAS),
.ahb_hreadyout (HREADYOUTS),
.ahb_hresp (HRESPS),
.drq_ipdma128 (exp_drq_ip_o),
.dlast_ipdma128 (1'b0),
.drq_opdma128 (exp_drq_op_o),
.dlast_opdma128 (1'b0),
.irq_key128 (exp_irq_o[0]),
.irq_ip128 (exp_irq_o[1]),
.irq_op128 (exp_irq_o[2]),
.irq_error (exp_irq_o[3]),
.irq_merged ( )
);
endmodule
system/aes/src/nanosoc_exp_wrapper.v deleted 100644 → 0
+ 0
− 76
View file @ fa7ecce0
//-----------------------------------------------------------------------------
// SoC Labs Basic Example Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module nanosoc_exp_wrapper #(
parameter AHBADDRWIDTH=16,
parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=128,
parameter CFGNUMIRQ=4
) (
input wire HCLK, // Clock
input wire HRESETn, // Reset
// AHB connection to Initiator
input wire HSEL_i,
input wire [AHBADDRWIDTH-1:0] HADDR_i,
input wire [1:0] HTRANS_i,
input wire [2:0] HSIZE_i,
input wire [3:0] HPROT_i,
input wire HWRITE_i,
input wire HREADY_i,
input wire [31:0] HWDATA_i,
output wire HREADYOUT_o,
output wire HRESP_o,
output wire [31:0] HRDATA_o,
// Input Data Request Signal to DMAC
output wire exp_drq_ip_o,
input wire exp_dlast_ip_i,
// Output Data Request Signal to DMAC
output wire exp_drq_op_o,
input wire exp_dlast_op_i,
// Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o
);
soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSEL_i),
.ahb_haddr16 (HADDR_i[15:0]),
.ahb_htrans (HTRANS_i),
.ahb_hwrite (HWRITE_i),
.ahb_hsize (HSIZE_i),
.ahb_hprot (HPROT_i),
.ahb_hwdata (HWDATA_i),
.ahb_hready (HREADY_i),
.ahb_hrdata (HRDATA_o),
.ahb_hreadyout (HREADYOUT_o),
.ahb_hresp (HRESP_o),
.drq_ipdma128 (exp_drq_ip_o),
.dlast_ipdma128 (1'b0),
.drq_opdma128 (exp_drq_op_o),
.dlast_opdma128 (1'b0),
.irq_key128 (exp_irq_o[0]),
.irq_ip128 (exp_irq_o[1]),
.irq_op128 (exp_irq_o[2]),
.irq_error (exp_irq_o[3]),
.irq_merged ( )
);
endmodule
system/aes/src/soclabs_ahb_aes128_ctrl.v deleted 100644 → 0
+ 0
− 583
View file @ fa7ecce0
This diff is collapsed.
system/aes/verif/aes128_log_to_file.v deleted 100644 → 0
+ 0
− 308
View file @ fa7ecce0
//-----------------------------------------------------------------------------
// AHB transaction logger, developed for DMA integration testing
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module aes128_log_to_file
#(parameter FILENAME = "aes128.log",
parameter TIMESTAMP = 1)
(
input wire ahb_hclk, // Clock
input wire ahb_hresetn, // Reset
input wire ahb_hsel, // Device select
input wire [15:0] ahb_haddr16, // Address for byte select
input wire [1:0] ahb_htrans, // Transfer control
input wire [2:0] ahb_hsize, // Transfer size
input wire [3:0] ahb_hprot, // Protection control
input wire ahb_hwrite, // Write control
input wire ahb_hready, // Transfer phase done
input wire [31:0] ahb_hwdata, // Write data
input wire ahb_hreadyout, // Device ready
input wire [31:0] ahb_hrdata, // Read data output
input wire ahb_hresp, // Device response
// stream data
input wire drq_ipdma128, // (to) DMAC input burst request
input wire dlast_ipdma128,// (from) DMAC input burst end (last transfer)
input wire drq_opdma128, // (to) DMAC output dma burst request
input wire dlast_opdma128,// (from) DMAC output burst end (last transfer)
input wire irq_key128,
input wire irq_ip128,
input wire irq_op128,
input wire irq_error,
input wire irq_merged // combined interrrupt request (to CPU)
);
// CORE ID
localparam ADDR_CORE_NAME0 = 16'h0000;
localparam ADDR_CORE_NAME1 = 16'h0004;
localparam ADDR_CORE_VERSION= 16'h0008;
localparam CORE_NAME0 = 32'h61657331; // "aes1"
localparam CORE_NAME1 = 32'h32382020; // "28 "
localparam CORE_VERSION = 32'h302e3031; // "0.01"
// CTRL control register with bit-set/bit-clear options
localparam ADDR_CTRL = 16'h0010;
localparam ADDR_CTRL_SET = 16'h0014;
localparam ADDR_CTRL_CLR = 16'h0018;
localparam CTRL_REG_WIDTH = 8;
localparam CTRL_BIT_MAX = (CTRL_REG_WIDTH-1);
localparam CTRL_KEY_REQ_BIT = 0;
localparam CTRL_IP_REQ_BIT = 1;
localparam CTRL_OP_REQ_BIT = 2;
localparam CTRL_ERR_REQ_BIT = 3;
localparam CTRL_KEYOK_BIT = 4;
localparam CTRL_VALID_BIT = 5;
localparam CTRL_BYPASS_BIT = 6;
localparam CTRL_ENCODE_BIT = 7;
// STAT status regisyer
localparam ADDR_STAT = 16'h001c;
localparam STAT_REG_WIDTH = 8;
localparam STAT_BIT_MAX = (STAT_REG_WIDTH-1);
localparam STAT_KEYREQ_BIT = 0;
localparam STAT_INPREQ_BIT = 1;
localparam STAT_OUTREQ_BIT = 2;
localparam STAT_ERROR_BIT = 3;
localparam STAT_KEYOK_BIT = 4;
localparam STAT_VALID_BIT = 5;
// QUAL qualifier field
localparam ADDR_QUAL = 16'h0020;
localparam QUAL_REG_WIDTH = 32;
localparam QUAL_BIT_MAX = (QUAL_REG_WIDTH-1);
// DREQ DMAC request control with bit-set/bit-clear options
localparam ADDR_DREQ = 16'h0030;
localparam ADDR_DREQ_SET = 16'h0034;
localparam ADDR_DREQ_CLR = 16'h0038;
localparam ADDR_DREQ_ACT = 16'h003c;
localparam DREQ_REG_WIDTH = 3;
localparam DREQ_BIT_MAX = (DREQ_REG_WIDTH-1);
localparam REQ_KEYBUF_BIT = 0;
localparam REQ_IP_BUF_BIT = 1;
localparam REQ_OP_BUF_BIT = 2;
// IREQ CPU interrupt request control with bit-set/bit-clear options
localparam ADDR_IREQ = 16'h0040;
localparam ADDR_IREQ_SET = 16'h0044;
localparam ADDR_IREQ_CLR = 16'h0048;
localparam ADDR_IREQ_ACT = 16'h004c;
localparam IREQ_REG_WIDTH = 4;
localparam IREQ_BIT_MAX = (IREQ_REG_WIDTH-1);
localparam REQ_ERROR_BIT = 3;
localparam ADDR_KEY_BASE = 16'h4000;
localparam ADDR_KEY0 = 16'h4000;
localparam ADDR_KEY3 = 16'h400c;
localparam ADDR_KEY7 = 16'h401c;
localparam ADDR_IBUF_BASE = 16'h8000;
localparam ADDR_IBUF_0 = 16'h8000;
localparam ADDR_IBUF_3 = 16'h800c;
localparam ADDR_OBUF_BASE = 16'hc000;
localparam ADDR_OBUF_3 = 16'hc00c;
// AHB transction de-pipelining
// --------------------------------------------------------------------------
// Internal regs/wires
// --------------------------------------------------------------------------
reg sel_r;
reg [15:0] addr16_r;
reg wcyc_r;
reg rcyc_r;
reg [3:0] byte4_r;
reg [3:0] dma_ctrl_state_r;
// --------------------------------------------------------------------------
// AHB slave byte buffer interface, support for unaligned data transfers
// --------------------------------------------------------------------------
wire [1:0] byte_addr = ahb_haddr16[1:0];
// generate next byte enable decodes for Word/Half/Byte CPU/DMA accesses
wire [3:0] byte_nxt;
assign byte_nxt[0] = (ahb_hsize[1])|((ahb_hsize[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b00);
assign byte_nxt[1] = (ahb_hsize[1])|((ahb_hsize[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b01);
assign byte_nxt[2] = (ahb_hsize[1])|((ahb_hsize[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b10);
assign byte_nxt[3] = (ahb_hsize[1])|((ahb_hsize[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b11);
// de-pipelined registered access signals
always @(posedge ahb_hclk or negedge ahb_hresetn)
if (!ahb_hresetn)
begin
addr16_r <= 16'h0000;
sel_r <= 1'b0;
wcyc_r <= 1'b0;
rcyc_r <= 1'b0;
byte4_r <= 4'b0000;
end else if (ahb_hready)
begin
addr16_r <= (ahb_hsel & ahb_htrans[1]) ? ahb_haddr16 : addr16_r;
sel_r <= (ahb_hsel & ahb_htrans[1]);
wcyc_r <= (ahb_hsel & ahb_htrans[1] & ahb_hwrite);
rcyc_r <= (ahb_hsel & ahb_htrans[1] & !ahb_hwrite);
byte4_r <= (ahb_hsel & ahb_htrans[1]) ? byte_nxt[3:0] : 4'b0000;
end
wire [31:0] ahb_hdata = (wcyc_r)? ahb_hwdata : ahb_hrdata;
//----------------------------------------------
//-- File I/O
//----------------------------------------------
integer fd; // channel descriptor for cmd file input
integer ch;
reg drq_ipdma128_prev;
reg dlast_ipdma128_prev;
reg drq_opdma128_prev;
reg dlast_opdma128_prev;
reg irq_key128_prev;
reg irq_ip128_prev;
reg irq_op128_prev;
reg irq_error_prev;
reg irq_merged_prev;
wire drq_ipdma128_change;
wire dlast_ipdma128_change;
wire drq_opdma128_change;
wire dlast_opdma128_change;
wire irq_key128_change;
wire irq_ip128_change;
wire irq_op128_change;
wire irq_error_change;
wire irq_merged_change;
wire irq_change;
wire drq_change;
wire any_change;
reg [31:0] cyc_count;
`define EOF -1
reg [7:0] ctrl_reg;
reg [2:0] dreq_reg;
reg [2:0] ireq_reg;
always @(posedge ahb_hclk or negedge ahb_hresetn)
if (!ahb_hresetn)
begin
drq_ipdma128_prev <= 1'b0;
dlast_ipdma128_prev <= 1'b0;
drq_opdma128_prev <= 1'b0;
dlast_opdma128_prev <= 1'b0;
irq_key128_prev <= 1'b0;
irq_ip128_prev <= 1'b0;
irq_op128_prev <= 1'b0;
irq_error_prev <= 1'b0;
irq_merged_prev <= 1'b0;
end else if (ahb_hready)
begin
drq_ipdma128_prev <= drq_ipdma128 ;
dlast_ipdma128_prev <= dlast_ipdma128;
drq_opdma128_prev <= drq_opdma128 ;
dlast_opdma128_prev <= dlast_opdma128;
irq_key128_prev <= irq_key128 ;
irq_ip128_prev <= irq_ip128 ;
irq_op128_prev <= irq_op128 ;
irq_error_prev <= irq_error ;
irq_merged_prev <= irq_merged ;
end
assign drq_ipdma128_change = (drq_ipdma128_prev ^ drq_ipdma128 );
assign dlast_ipdma128_change = (dlast_ipdma128_prev ^ dlast_ipdma128);
assign drq_opdma128_change = (drq_opdma128_prev ^ drq_opdma128 );
assign dlast_opdma128_change = (dlast_opdma128_prev ^ dlast_opdma128);
assign drq_change = drq_ipdma128_change | drq_opdma128_change
| dlast_ipdma128_change | dlast_opdma128_change;
assign irq_key128_change = (irq_key128_prev ^ irq_key128 );
assign irq_ip128_change = (irq_ip128_prev ^ irq_ip128 );
assign irq_op128_change = (irq_op128_prev ^ irq_op128 );
assign irq_error_change = (irq_error_prev ^ irq_error );
assign irq_change = irq_key128_change | irq_ip128_change
| irq_op128_change | irq_error_change;
assign any_change = drq_ipdma128_change
| dlast_ipdma128_change
| drq_opdma128_change
| dlast_opdma128_change
| irq_key128_change
| irq_ip128_change
| irq_op128_change
| irq_error_change
| irq_merged_change
;
initial
begin
fd= $fopen(FILENAME,"w");
cyc_count <= 0;
if (fd == 0)
$write("** %m : output log file failed to open **\n");
else begin
@(posedge ahb_hresetn);
while (1) begin
@(posedge ahb_hclk);
cyc_count <= cyc_count +1;
if (sel_r & ahb_hready) begin
$fwrite(fd, "AES-C: ");
case ({addr16_r[15:2],2'b00})
ADDR_CORE_NAME0 : begin $fwrite(fd, "CORE_NAME0 "); end
ADDR_CORE_NAME1 : begin $fwrite(fd, "CORE_NAME1 "); end
ADDR_CORE_VERSION : begin $fwrite(fd, "CORE_VERSION"); end
ADDR_CTRL : begin $fwrite(fd, "CTRL "); if (wcyc_r) ctrl_reg <= ahb_hwdata[7:0]; end
ADDR_CTRL_SET : begin $fwrite(fd, "CTRL_SET "); if (wcyc_r) ctrl_reg <= ctrl_reg | ahb_hwdata[7:0]; end
ADDR_CTRL_CLR : begin $fwrite(fd, "CTRL_CLR "); if (wcyc_r) ctrl_reg <= ctrl_reg &~ahb_hwdata[7:0]; end
ADDR_STAT : begin $fwrite(fd, "STAT "); end
ADDR_QUAL : begin $fwrite(fd, "QUAL "); end
ADDR_DREQ : begin $fwrite(fd, "DREQ "); if (wcyc_r) dreq_reg <= ahb_hwdata[2:0]; end
ADDR_DREQ_SET : begin $fwrite(fd, "DREQ_SET "); if (wcyc_r) dreq_reg <= dreq_reg | ahb_hwdata[2:0]; end
ADDR_DREQ_CLR : begin $fwrite(fd, "DREQ_CLR "); if (wcyc_r) dreq_reg <= dreq_reg &~ahb_hwdata[2:0]; end
ADDR_DREQ_ACT : begin $fwrite(fd, "DREQ_ACT "); end
ADDR_IREQ : begin $fwrite(fd, "IREQ "); end
ADDR_IREQ_SET : begin $fwrite(fd, "IREQ_SET "); if (wcyc_r) ireq_reg <= ahb_hwdata[3:0]; end
ADDR_IREQ_CLR : begin $fwrite(fd, "IREQ_CLR "); if (wcyc_r) ireq_reg <= ireq_reg | ahb_hwdata[3:0]; end
ADDR_IREQ_ACT : begin $fwrite(fd, "IREQ_ACT "); if (wcyc_r) ireq_reg <= ireq_reg &~ahb_hwdata[3:0]; end
default:
if (addr16_r[15:14] == 2'b01) $fwrite(fd, "KEYBUF128 ");
else if (addr16_r[15:14] == 2'b10) $fwrite(fd, "IPBUF128 ");
else if (addr16_r[15:14] == 2'b11) $fwrite(fd, "OPBUF128 ");
endcase
$fwrite(fd, " A+0x%04x, %s, D=0x", addr16_r, (wcyc_r) ? "W" : "R");
if (byte4_r[3]) $fwrite(fd, "%02x", ahb_hdata[31:24]); else $fwrite(fd, "--");
if (byte4_r[2]) $fwrite(fd, "%02x", ahb_hdata[23:16]); else $fwrite(fd, "--");
if (byte4_r[1]) $fwrite(fd, "%02x", ahb_hdata[15: 8]); else $fwrite(fd, "--");
if (byte4_r[0]) $fwrite(fd, "%02x", ahb_hdata[ 7: 0]); else $fwrite(fd, "--");
if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n", cyc_count, $time); else $fwrite(fd, "\n");
end
if (any_change) begin
$fwrite(fd, "AESRQ: ");
if (drq_change) begin
$fwrite(fd, " drq_ipdma128=%b,",drq_ipdma128);
$fwrite(fd, " dlast_ipdma128=%b,",dlast_ipdma128);
$fwrite(fd, " drq_opdma128=%b,",drq_opdma128);
$fwrite(fd, " dlast_opdma128=%b",dlast_opdma128);
end
if (irq_change) begin
if (drq_change) $fwrite(fd, ",");
$fwrite(fd, " irq_merged=%b,",irq_merged);
$fwrite(fd, "irq_key128=%b,",irq_key128);
$fwrite(fd, "irq_ip128=%b,",irq_ip128);
$fwrite(fd, "irq_op128=%b,",irq_op128);
$fwrite(fd, "irq_error=%b",irq_error);
end
if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n",cyc_count, $time); else $fwrite(fd, "\n");
end
end
$fclose(fd);
end
end
endmodule
system/defines/pl230_defs.v deleted 100644 → 0
+ 0
− 189
View file @ fa7ecce0
//-----------------------------------------------------------------------------
// NanoSoC customised Cortex-M0 controller DMA230 configuration
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright � 2021, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
// (C) COPYRIGHT 2006-2007 ARM Limited.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//
// File Name : pl230_defs.v
// Checked In : $Date: 2007-06-06 21:55:22 +0530 (Wed, 06 Jun 2007) $
// Revision : $Revision: 13823 $
// State : $state: PL230-DE-98007-r0p0-02rel0 $
//
//-----------------------------------------------------------------------------
// Purpose : Peripheral specific macro definitions
//
//-----------------------------------------------------------------------------
`ifdef ARM_TIMESCALE_DEFINED
`timescale 1ns/1ps
`endif
// Set the number of channels implemented
`define PL230_CHNLS 2
`define PL230_CHNL_BITS 1
//`define PL230_ONE_CHNL
// Include Integration Test Logic
`define PL230_INCLUDE_TEST
// AHB Interface
`define PL230_AHB_TRANS_IDLE 2'b00
`define PL230_AHB_TRANS_NONSEQ 2'b10
`define PL230_AHB_READ 1'b0
`define PL230_AHB_WRITE 1'b1
`define PL230_AHB_SIZE_BYTE 3'b000
`define PL230_AHB_SIZE_HWORD 3'b001
`define PL230_AHB_SIZE_WORD 3'b010
// PrimeCell Configuration
`define PL230_PERIPH_ID_0 8'h30
`define PL230_PERIPH_ID_1 8'hB2
`define PL230_PERIPH_ID_2 8'h0B
`define PL230_PERIPH_ID_3 8'h00
`define PL230_PERIPH_ID_4 8'h04
`define PL230_PCELL_ID_0 8'h0D
`define PL230_PCELL_ID_1 8'hF0
`define PL230_PCELL_ID_2 8'h05
`define PL230_PCELL_ID_3 8'hB1
// Memory Mapped Registers
// Controller Configuration Registers
`define PL230_ADDR_DMA_STATUS 12'h000
`define PL230_ADDR_DMA_CFG 12'h004
`define PL230_ADDR_CTRL_BASE_PTR 12'h008
`define PL230_ADDR_ALT_CTRL_BASE_PTR 12'h00C
`define PL230_ADDR_DMA_WAITONREQ_STATUS 12'h010
`define PL230_ADDR_CHNL_SW_REQUEST 12'h014
`define PL230_ADDR_CHNL_USEBURST_SET 12'h018
`define PL230_ADDR_CHNL_USEBURST_CLR 12'h01C
`define PL230_ADDR_CHNL_REQ_MASK_SET 12'h020
`define PL230_ADDR_CHNL_REQ_MASK_CLR 12'h024
`define PL230_ADDR_CHNL_ENABLE_SET 12'h028
`define PL230_ADDR_CHNL_ENABLE_CLR 12'h02C
`define PL230_ADDR_CHNL_PRI_ALT_SET 12'h030
`define PL230_ADDR_CHNL_PRI_ALT_CLR 12'h034
`define PL230_ADDR_CHNL_PRIORITY_SET 12'h038
`define PL230_ADDR_CHNL_PRIORITY_CLR 12'h03C
// Reserved 12'h040
// Reserved 12'h044
// Reserved 12'h048
`define PL230_ADDR_ERR_CLR 12'h04C
// Integration Test Registers
`define PL230_ADDR_INTEGRATION_CFG 12'hE00
// Reserved 12'hE04
`define PL230_ADDR_STALL_STATUS 12'hE08
// Reserved 12'hE0C
`define PL230_ADDR_DMA_REQ_STATUS 12'hE10
// Reserved 12'hE14
`define PL230_ADDR_DMA_SREQ_STATUS 12'hE18
// Reserved 12'hE1C
`define PL230_ADDR_DMA_DONE_SET 12'hE20
`define PL230_ADDR_DMA_DONE_CLR 12'hE24
`define PL230_ADDR_DMA_ACTIVE_SET 12'hE28
`define PL230_ADDR_DMA_ACTIVE_CLR 12'hE2C
// Reserved 12'hE30
// Reserved 12'hE34
// Reserved 12'hE38
// Reserved 12'hE3C
// Reserved 12'hE40
// Reserved 12'hE44
`define PL230_ADDR_ERR_SET 12'hE48
// Reserved 12'hE4C
// PrimeCell Configuration Registers
`define PL230_ADDR_PERIPH_ID_4 12'hFD0
// Reserved 12'hFD4
// Reserved 12'hFD8
// Reserved 12'hFDC
`define PL230_ADDR_PERIPH_ID_0 12'hFE0
`define PL230_ADDR_PERIPH_ID_1 12'hFE4
`define PL230_ADDR_PERIPH_ID_2 12'hFE8
`define PL230_ADDR_PERIPH_ID_3 12'hFEC
`define PL230_ADDR_PCELL_ID_0 12'hFF0
`define PL230_ADDR_PCELL_ID_1 12'hFF4
`define PL230_ADDR_PCELL_ID_2 12'hFF8
`define PL230_ADDR_PCELL_ID_3 12'hFFC
// Bit vector definitions for channel_cfg
`define PL230_CHANNEL_CFG_BITS 20
// Destination address increment
`define PL230_CHANNEL_CFG_DST_INC channel_cfg[19:18]
`define PL230_HRDATA_DST_INC hrdata[31:30]
// Destination transfer size
// Source and destination sizes must match
// so the same bits as the src_size are used
`define PL230_CHANNEL_CFG_DST_SIZE channel_cfg[15:14]
`define PL230_HRDATA_DST_SIZE hrdata[29:28]
// Source address increment
`define PL230_CHANNEL_CFG_SRC_INC channel_cfg[17:16]
`define PL230_HRDATA_SRC_INC hrdata[27:26]
// Source transfer size
`define PL230_CHANNEL_CFG_SRC_SIZE channel_cfg[15:14]
`define PL230_HRDATA_SRC_SIZE hrdata[25:24]
// Destination AHB protection control
`define PL230_CHANNEL_CFG_DST_PROT_CTRL channel_cfg[13:11]
`define PL230_HRDATA_DST_PROT_CTRL hrdata[23:21]
// Source AHB protection control
`define PL230_CHANNEL_CFG_SRC_PROT_CTRL channel_cfg[10:8]
`define PL230_HRDATA_SRC_PROT_CTRL hrdata[20:18]
// Power of two transactions per request
`define PL230_CHANNEL_CFG_R channel_cfg[7:4]
`define PL230_HRDATA_R hrdata[17:14]
// Number of bits in the N counter - hrdata[13:4]
`define PL230_N_COUNT_BITS 10
// Lsb bit offset for n_minus_1
`define PL230_N_COUNT_OFFSET 4
// Set chnl_useburst_status
`define PL230_CHANNEL_CFG_NEXT_USEBURST channel_cfg[3]
`define PL230_HRDATA_NEXT_USEBURST hrdata[3]
// DMA cycle control
`define PL230_CHANNEL_CFG_CYCLE_CTRL channel_cfg[2:0]
`define PL230_HRDATA_CYCLE_CTRL hrdata[2:0]
// Number of bits for the statemachine
`define PL230_STATE_BITS 4
// Statemachine state encoding
`define PL230_ST_IDLE 4'h0
`define PL230_ST_RD_CTRL 4'h1
`define PL230_ST_RD_SPTR 4'h2
`define PL230_ST_RD_DPTR 4'h3
`define PL230_ST_RD_SDAT 4'h4
`define PL230_ST_WR_DDAT 4'h5
`define PL230_ST_WAIT 4'h6
`define PL230_ST_WR_CTRL 4'h7
`define PL230_ST_STALL 4'h8
`define PL230_ST_DONE 4'h9
`define PL230_ST_PSGP 4'hA
`define PL230_ST_RESVD_0 4'hB
`define PL230_ST_RESVD_1 4'hC
`define PL230_ST_RESVD_2 4'hD
`define PL230_ST_RESVD_3 4'hE
`define PL230_ST_RESVD_4 4'hF
`define PL230_SIZE_BYTE 2'b00
`define PL230_SIZE_HWORD 2'b01
`define PL230_SIZE_WORD 2'b10
`define PL230_SIZE_RESVD 2'b11
// pl230_defs.v end
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment