update zcu104 fpga target build ready for extio integraion

fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl

 
 ################################################################
-# This is a generated script based on design: nanosoc_design
+# This is a generated script based on design: design_1
 #
 # Though there are limitations about the generated script,
 # the main purpose of this utility is to make learning
@@ -35,7 +35,7 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
 ################################################################
 
 # To test this script, run the following commands from Vivado Tcl console:
-# source nanosoc_design_script.tcl
+# source design_1_script.tcl
 
 set bCheckIPsPassed 1
 ##################################################################
@@ -154,7 +154,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   # Create instance: axi_bram_ctrl_0, and set properties
   set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
   set_property -dict [ list \
-   CONFIG.ECC_TYPE {0} \
+   CONFIG.ECC_TYPE {Hamming} \
    CONFIG.PROTOCOL {AXI4} \
    CONFIG.SINGLE_PORT_BRAM {1} \
  ] $axi_bram_ctrl_0
@@ -190,13 +190,13 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   # Create instance: axi_uartlite_0, and set properties
   set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
   set_property -dict [ list \
-   CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+   CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
  ] $axi_uartlite_0
 
   # Create instance: axi_uartlite_1, and set properties
   set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
   set_property -dict [ list \
-   CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+   CONFIG.C_S_AXI_ACLK_FREQ_HZ {20000000} \
  ] $axi_uartlite_1
 
   # Create instance: axis_data_fifo_0, and set properties
@@ -248,14 +248,14 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   # Create instance: ft1248x1_to_axi_stream_0, and set properties
   set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
 
-  # Create instance: p1_i_bit15to6, and set properties
-  set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+  # Create instance: p1_i_bit15to8, and set properties
+  set p1_i_bit15to8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to8 ]
   set_property -dict [ list \
    CONFIG.DIN_FROM {15} \
-   CONFIG.DIN_TO {6} \
+   CONFIG.DIN_TO {8} \
    CONFIG.DIN_WIDTH {16} \
-   CONFIG.DOUT_WIDTH {10} \
- ] $p1_i_bit15to6
+   CONFIG.DOUT_WIDTH {8} \
+ ] $p1_i_bit15to8
 
   # Create instance: p1_i_concat, and set properties
   set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
@@ -266,10 +266,10 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
    CONFIG.IN3_WIDTH {1} \
    CONFIG.IN4_WIDTH {1} \
    CONFIG.IN5_WIDTH {1} \
-   CONFIG.IN6_WIDTH {10} \
+   CONFIG.IN6_WIDTH {1} \
    CONFIG.IN7_WIDTH {1} \
    CONFIG.IN8_WIDTH {8} \
-   CONFIG.NUM_PORTS {7} \
+   CONFIG.NUM_PORTS {9} \
  ] $p1_i_concat
 
   # Create instance: p1_o_bit1, and set properties
@@ -429,15 +429,15 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
   connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
   connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
-  connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+  connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to8/Din]
   connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
   connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
   connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
   connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
   connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
   connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
-  connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
-  connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+  connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins p1_i_concat/In6] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins p1_i_concat/In7] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
   connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
   connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
   connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
@@ -445,7 +445,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
   connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
   connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
-  connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+  connect_bd_net -net p1_i_bit15to8_Dout [get_bd_pins p1_i_bit15to8/Dout] [get_bd_pins p1_i_concat/In8]
   connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
   connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
   connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
@@ -1111,7 +1111,7 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 
   # Create address segments
   assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force