and add matric build log file for reference

Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/soclabs_ahb32_4x7.log

@@ -14,7 +14,7 @@
 =
 = BuildBusMatrix.pl
 =
-= Run Date : 10/02/2023 10:12:02
+= Run Date : 28/02/2023 19:03:25
 ==============================================================
 
 Script accepted the following parameters:
@@ -34,7 +34,7 @@ Script accepted the following parameters:
  - Routing data width      : 32
  - Routing address width   : 32
  - User signal width       : 2
- - Timescales              : yes (default)
+ - Timescales              : no
  - Configuration directory : './verilog/built'
  - Source directory        : './verilog/src'
  - IPXact target directory : 'ipxact/built'
@@ -44,31 +44,43 @@ Script accepted the following parameters:
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v' file...
-Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_exp.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_ram2.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_ram3.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_ram8.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_ram9.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_rom1.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter_sys.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v' file...
 Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v' file...
-Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_exp.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_ram2.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_ram3.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_ram8.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_ram9.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_rom1.v' file...
+Deleting the './verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput_sys.v' file...
 
 Deleting the 'ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.xml' file...
 Deleting the 'ipxact/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.xml' file...
 
 Creating the bus matrix variant...
 
- - Rendering 'soclabs_4x7_AhbMatrix_lite.xml'
- - Rendering 'soclabs_4x7_MatrixDecode_adp.v'
+ - Rendering 'soclabs_4x7_AhbMatrix_default_slave.v'
+ - Rendering 'soclabs_4x7_AhbMatrix_lite.v'
  - Rendering 'soclabs_4x7_AhbMatrix.v'
- - Rendering 'soclabs_4x7_MatrixDecode_dma2.v'
  - Rendering 'soclabs_4x7_MasterInput.v'
- - Rendering 'soclabs_4x7_AhbMatrix_lite.v'
- - Rendering 'soclabs_4x7_MatrixDecode_dma.v'
  - Rendering 'soclabs_4x7_SlaveOutput.v'
- - Rendering 'soclabs_4x7_AhbMatrix_default_slave.v'
  - Rendering 'soclabs_4x7_AhbMatrix.xml'
  - Rendering 'soclabs_4x7_Arbiter.v'
+ - Rendering 'soclabs_4x7_MatrixDecode_adp.v'
  - Rendering 'soclabs_4x7_MatrixDecode_cpu.v'
+ - Rendering 'soclabs_4x7_MatrixDecode_dma2.v'
+ - Rendering 'soclabs_4x7_AhbMatrix_lite.xml'
+ - Rendering 'soclabs_4x7_MatrixDecode_dma.v'
 
 Done!