FPGA drivers update + DMA + watchdog

fpga/ci_tools/drivers/ADP_PYNQ_driver.py

+from time import sleep, time
+from pynq import MMIO
+
+class ADP:
+    def __init__(self, address):
+        # HARDWARE CONSTANTS
+        self.RX_FIFO = 0x00
+        self.TX_FIFO = 0x04
+        # Status Reg
+        self.STAT_REG = 0x08
+        self.RX_VALID = 0
+        self.RX_FULL = 1
+        self.TX_EMPTY = 2
+        self.TX_FULL = 3
+        self.IS_INTR = 4
+
+        # Ctrl Reg
+        self.CTRL_REG = 0x0C
+        self.RST_TX = 0
+        self.RST_RX = 1
+        self.INTR_EN = 4
+        # Setup axi core
+        self.uart = MMIO(address, 0x10000, debug=False)
+        self.address = address
+
+    def setupCtrlReg(self):
+#        # Reset FIFOs, disable interrupts
+#        self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)
+#        sleep(1)
+        self.uart.write(self.CTRL_REG, 0)
+        sleep(1)
+
+    def monitorModeEnter(self):
+        self.uart.write(self.TX_FIFO, 0x1b)
+
+    def monitorModeExit(self):
+        self.uart.write(self.TX_FIFO, 0x04)
+
+    ##################################################################
+    # read: Read a block from the Rx FIFO
+    ##################################################################
+    def read(self, length):
+        # status = currentStatus(uart) bad idea
+        buf = ""
+        timeout=1
+        stop_time = time() + timeout
+        for i in range(length):
+            # Wait till RX fifo has valid data, stop waiting if timeoutpasses
+            while (not (self.uart.read(self.STAT_REG) & 1 << self.RX_VALID)) and (time() < stop_time):
+                pass
+            if time() >= stop_time:
+                break
+            buf += chr(self.uart.read(self.RX_FIFO))
+            stop_time = time() + timeout
+
+        return buf
+
+    ##################################################################
+    # write: Write a block of data to the Tx FIFO
+    ##################################################################
+    def write(self, buf):
+        # Write bytes via UART
+        timeout=1
+        stop_time = time() + timeout
+        wr_count = 0
+        for i in buf:
+            # Wait while TX FIFO is Full, stop waiting if timeout passes
+            while (self.uart.read(self.STAT_REG) & 1 << self.TX_FULL) and (time() < stop_time):
+                pass
+            # Check timeout
+            if time() > stop_time:
+                wr_count = -1
+                break
+            self.uart.write(self.TX_FIFO, ord(i))
+            wr_count += 1
+            stop_time = time() + timeout
+        return wr_count
+    ##################################################################
+    # readLine: Read a block from the Rx FIFO until newline character
+    ##################################################################
+    def readLine(self):
+        buf = ""
+        timeout = 1
+        stop_time = time() + timeout
+        stop=False
+        while(not(stop)):
+            while(not(self.checkReg(self.STAT_REG) & 1 << self.RX_VALID) and (time() < stop_time)):
+                pass
+            if time() > stop_time:
+                break
+            next_chr = chr(self.uart.read(self.RX_FIFO))
+            buf += next_chr
+            stop_time = time() + timeout
+            if (next_chr == '\n'):
+                stop = True
+        return buf
+    def write8(self, buf):
+        # Write bytes via UART
+        timeout=1
+        stop_time = time() + timeout
+        wr_count = 0
+        while (self.uart.read(self.STAT_REG) & 1 << self.TX_FULL) and (time() < stop_time):
+            pass
+        # Check timeout
+        if time() > stop_time:
+            wr_count = -1
+        self.uart.write(self.TX_FIFO, buf)
+        wr_count += 1
+        stop_time = time() + timeout
+        return wr_count
+    
+    
\ No newline at end of file

fpga/ci_tools/drivers/NanoSoC_Verification.py

 import os, sys
 from progress.bar import Bar
-if os.environ["BOARDNAME"] == 'MPS3':
+if os.environ["BOARD"] == 'MPS3':
     from .ADP_UART_driver import ADP
+elif os.environ["BOARD"] == "ZCU104":
+    from .ADP_PYNQ_driver import ADP
 
 class NanoSoC_APD:
     def __init__(self):

fpga/ci_tools/load_bitfile.py

@@ -2,7 +2,7 @@ import os, warnings
 from pynq import PL
 from pynq import Overlay
 
-ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/nanosoc_design.bit")
 
 if not os.path.exists(PL.bitfile_name):
     warnings.warn('There is no overlay loaded after boot.', UserWarning)

fpga/ci_tools/romtable_test.py

@@ -4,7 +4,7 @@ from drivers.NanoSoC_Verification import NanoSoC_APD
 
 
 NanoSoC = NanoSoC_APD()
-NanoSoC.writeHex('uart_tests.hex')
+NanoSoC.writeHex('binaries/uart_tests.hex')
 print(NanoSoC.adp.read(500))
 NanoSoC.adp.write('C 0x200\n')
 NanoSoC.adp.write('C 0x201\n')

fpga/ci_tools/run_full_verification.py

 import os, warnings
 from pynq import PL
 from pynq import Overlay
+import os
+from drivers.NanoSoC_Verification import NanoSoC_APD
 
-ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
+log = open("verification_log",'w')
+tests = open("fpga_tests",'r')
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/nanosoc_design.bit")
 
 if not os.path.exists(PL.bitfile_name):
     warnings.warn('There is no overlay loaded after boot.', UserWarning)
@@ -13,7 +17,34 @@ ol.download()
 
 if ol.is_loaded():
 	print("Overlay Loaded")
+	log.write("Overlay Load Test: PASSED\n")
+	NanoSoC = NanoSoC_APD()
+	for lines in tests:
+		ol.download()
+		NanoSoC = NanoSoC_APD()
+		li=lines.strip()
+		li=li.lstrip('nanosoc_tech/testcodes/')
+		li = li.split('/')
+		testname = li[0]
+		testfile = li[1]
+		print("Running test: " + testfile)
+		NanoSoC.writeHex("binaries/" + testfile)
+		print(NanoSoC.adp.read(500))
+		NanoSoC.adp.write('C 0x200\n')
+		NanoSoC.adp.write('C 0x201\n')
+		buf = (NanoSoC.adp.read(1000000))
+		print(buf)
+		if "PASSED" in buf:
+			log.write(testfile + ": PASSED\n")
+		elif "SKIPPED" in buf:
+			log.write(testfile + ": SKIPPED\n")
+		else:
+			log.write(testfile + ": FAILED\n")
 else:
 	print("Overlay failed to load")
+	log.write("Overlay Load Test: FAILED\n")
+print("ALL TESTS FINISHED")
+log.close()
+
 
 

nanosoc/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v

@@ -9,6 +9,7 @@
 //
 // Copyright 2021-3, SoC Labs (www.soclabs.org)
 //-----------------------------------------------------------------------------
+`include "gen_defines.v"
 
 module nanosoc_ss_dma #(
     parameter    SYS_ADDR_W         = 32,  // System Address Width

software/common/demos/watchdog_demo.c

@@ -308,21 +308,22 @@ void NMI_Handler(void)
 /* Watchdog initialization */
 void watchdog_init(unsigned int cycle, int type)
 {
-  puts   ("  Unlocking watchdog...");
+  //puts   ("  Unlocking watchdog...");
   watchdog_unlock();
   CMSDK_WATCHDOG->LOAD = cycle;
   if (type==0) {
-    puts   ("  Set to no action");
+    //puts   ("  Set to no action");
     CMSDK_WATCHDOG->CTRL = 0;
   } else if (type==1) {
-    puts   ("  Set to NMI generation");
+    //puts   ("  Set to NMI generation");
     CMSDK_WATCHDOG->CTRL = CMSDK_Watchdog_CTRL_INTEN_Msk;
   } else {
-    puts   ("  Set to reset generation");
+    //puts   ("  Set to reset generation");
     CMSDK_WATCHDOG->CTRL = CMSDK_Watchdog_CTRL_RESEN_Msk|CMSDK_Watchdog_CTRL_INTEN_Msk;
   }
-  puts   ("  Locking watchdog...");
   watchdog_lock();
+  //puts   ("  Locking watchdog...");
+
 }
 /* ----------------------------------------------------------------- */
 /* Update watchdog counter */