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SoCLabs
NanoSoC Tech
Commits
d60d0d31
Commit
d60d0d31
authored
2 years ago
by
dam1n19
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Updated ROM Remap logic
parent
92bc2c00
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1 merge request
!1
changed imem to rom to allow initial program loading, updated bootloader code...
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system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+3
-3
3 additions, 3 deletions
system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
with
3 additions
and
3 deletions
system/nanosoc_interconnect/verilog/nanosoc_interconnect.v
+
3
−
3
View file @
d60d0d31
...
@@ -73,7 +73,7 @@ module nanosoc_interconnect #(
...
@@ -73,7 +73,7 @@ module nanosoc_interconnect #(
//--------------------------------
//--------------------------------
// CPU_0
// CPU_0
//--------------------------------
//--------------------------------
//
AHB -
Connectivity
// Connectivity
-AHB
wire
[
31
:
0
]
HADDR_CPU_0
;
wire
[
31
:
0
]
HADDR_CPU_0
;
wire
[
1
:
0
]
HTRANS_CPU_0
;
wire
[
1
:
0
]
HTRANS_CPU_0
;
wire
HWRITE_CPU_0
;
wire
HWRITE_CPU_0
;
...
@@ -161,8 +161,8 @@ module nanosoc_interconnect #(
...
@@ -161,8 +161,8 @@ module nanosoc_interconnect #(
.
HCLK
(
HCLK
),
.
HCLK
(
HCLK
),
.
HRESETn
(
HRESETn
),
.
HRESETn
(
HRESETn
),
// System Address Remap CO
n
trol
// System Address Remap CO
o
trol
.
REMAP
(
REMAP
),
.
REMAP
(
{
3'b0
,
!
ROM_
REMAP
}
),
// Manager Input Signals for SoCDebug Controller - Instantiated at Chip Level
// Manager Input Signals for SoCDebug Controller - Instantiated at Chip Level
.
HADDR_SOCDEBUG
(
HADDR32_SOCDEBUG_o
),
.
HADDR_SOCDEBUG
(
HADDR32_SOCDEBUG_o
),
...
...
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