update the FPGA top level for extio controller

fpga/targets/pynq_zcu104/vivado_script/2021_1/nanosoc_design.tcl

@@ -45,6 +45,7 @@ set bCheckIPs 1
 if { $bCheckIPs == 1 } {
    set list_check_ips "\ 
 soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:xlconstant:1.1\
 xilinx.com:ip:zynq_ultra_ps_e:3.3\
 xilinx.com:ip:axi_gpio:2.0\
 soclabs.org:user:axi_stream_io:1.0\
@@ -55,7 +56,6 @@ xilinx.com:ip:xlconcat:2.1\
 xilinx.com:ip:xlslice:1.0\
 xilinx.com:ip:proc_sys_reset:5.0\
 xilinx.com:ip:smartconnect:1.0\
-xilinx.com:ip:xlconstant:1.1\
 "
 
    set list_ips_missing ""
@@ -273,11 +273,11 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
    CONFIG.NUM_SI {1} \
  ] $smartconnect_0
 
-  # Create instance: xlconstant_0, and set properties
-  set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+  # Create instance: xlconst_zero, and set properties
+  set xlconst_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconst_zero ]
   set_property -dict [ list \
    CONFIG.CONST_VAL {0} \
- ] $xlconstant_0
+ ] $xlconst_zero
 
   # Create instance: xlconstant_1, and set properties
   set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
@@ -307,7 +307,7 @@ proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
   connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
   connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
   connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit0_ioreq1/Din] [get_bd_pins p1_o_bit1_ioreq2/Din] [get_bd_pins p1_o_bit3_iodatata4/Din]
-  connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_0/dout]
+  connect_bd_net -net const0 [get_bd_pins extio8x4_axis_target_0/testmode] [get_bd_pins p1_extio_concat_o/In0] [get_bd_pins p1_extio_concat_o/In1] [get_bd_pins p1_extio_concat_o/In4] [get_bd_pins p1_extio_concat_z/In2] [get_bd_pins p1_extio_concat_z/In4] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In3] [get_bd_pins pmoda_z_concat8/In4] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconst_zero/dout]
   connect_bd_net -net const1 [get_bd_pins p1_extio_concat_z/In0] [get_bd_pins p1_extio_concat_z/In1] [get_bd_pins xlconstant_1/dout]
   connect_bd_net -net extio8x4_axis_target_0_ioack_o [get_bd_pins extio8x4_axis_target_0/ioack_o] [get_bd_pins p1_extio_concat_o/In2]
   connect_bd_net -net extio8x4_axis_target_0_iodata4_o [get_bd_pins extio8x4_axis_target_0/iodata4_o] [get_bd_pins p1_extio_concat_o/In3]
@@ -375,6 +375,19 @@ proc create_root_design { parentCell } {
   # Create instance: nanosoc_chip_0, and set properties
   set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
 
+  # Create instance: xlconstant_zero, and set properties
+  set xlconstant_zero [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zero ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+ ] $xlconstant_zero
+
+  # Create instance: xlconstant_zerox4, and set properties
+  set xlconstant_zerox4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_zerox4 ]
+  set_property -dict [ list \
+   CONFIG.CONST_VAL {0} \
+   CONFIG.CONST_WIDTH {4} \
+ ] $xlconstant_zerox4
+
   # Create instance: zynq_ultra_ps_e_0, and set properties
   set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
   set_property -dict [ list \
@@ -1912,7 +1925,9 @@ Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD05000
   connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
   connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
   connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
-  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+  connect_bd_net -net xlconstant_zero_dout [get_bd_pins nanosoc_chip_0/alt_mode] [get_bd_pins nanosoc_chip_0/bist_enable] [get_bd_pins nanosoc_chip_0/bist_mode] [get_bd_pins nanosoc_chip_0/diag_ctrl] [get_bd_pins nanosoc_chip_0/diag_mode] [get_bd_pins nanosoc_chip_0/scan_enable] [get_bd_pins nanosoc_chip_0/scan_mode] [get_bd_pins nanosoc_chip_0/swd_mode] [get_bd_pins nanosoc_chip_0/test_i] [get_bd_pins nanosoc_chip_0/uart_rxd_i] [get_bd_pins xlconstant_zero/dout]
+  connect_bd_net -net xlconstant_zerox4_dout [get_bd_pins nanosoc_chip_0/bist_in] [get_bd_pins nanosoc_chip_0/scan_in] [get_bd_pins xlconstant_zerox4/dout]
+  connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
 
   # Create address segments
   assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force