Prepare to merge the AES128 integration and PL230 DMA driver support with main

.gitlab-ci.yml

@@ -24,47 +24,51 @@ stages:          # List of stages for jobs, and their order of execution
 build-job:       # This job runs in the build stage, which runs first.
   stage: build
   script:
-    - source /tools/Xilinx/Vivado/2021.2/.settings64-Vivado.sh
-    - cd ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/
-#    - source ./build_fpga_pynq_z2.scr
-#    - FILE = ./ ./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit 
-#    - if test -f "$FILE"; then
-#    -   echo "Build successful"
-#    - else
-#    -   echo "Build failed"
-#    - fi
-    - ls ../../../../../../arm-AAA-ip/
-    - ls ../../../../../../arm-AAA-ip/Cortex-M0/
-    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/
-    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical
-    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/
-    - ls ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-50000-r0p0-03rel2/logical/cortexm0_integration/verilog/
+    - source /tools/Xilinx/Vivado/2021.1/.settings64-Vivado.sh
+    - cp -r /home/gitlab-runner/arm-AAA-ip ../arm-AAA-ip
+    - cd ../arm-AAA-ip/Corstone-101_Foundation_IP/
+    - tar -xf BP210-r1p1-00rel0.tar.gz
+    - cd ../Cortex-M0/
+    - tar -xf AT510-r0p0-03rel2.tar.gz
+    - cd ../DMA-230_MicroDMA_Controller/
+    - tar -xf PL230-r0p0-02rel2-1.tar.gz
+    - cd ../../nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/
+    - if source ./build_fpga_pynq_z2.scr; then
+    -   FILE = ./pynq_export/pz2/pynq/overlays/soclabs/design_1.bit 
+    -   if test -f "$FILE"; then
+    -     echo "Build successful"
+    -   else
+    -     echo "Build failed"
+    -   fi
+    - fi
+    - cd ../../../../../../
+    - rm -r arm-AAA-ip
   tags:
-    - FPGA
+    - Vivado2021.1
 
-unit-test-job:   # This job runs in the test stage.
-  stage: test    # It only starts when the job in the build stage completes successfully.
-  script:
-    - echo "Running unit tests... This will take about 60 seconds."
-    - sleep 60
-    - echo "Code coverage is 90%"
-  tags:
-    - FPGA
+#unit-test-job:   # This job runs in the test stage.
+#  stage: test    # It only starts when the job in the build stage completes successfully.
+#  script:
+#    - echo "Running unit tests... This will take about 60 seconds."
+#    - sleep 60
+#    - echo "Code coverage is 90%"
+#  tags:
+#    - FPGA
 
-lint-test-job:   # This job also runs in the test stage.
-  stage: test    # It can run at the same time as unit-test-job (in parallel).
-  script:
-    - echo "Linting code... This will take about 10 seconds."
-    - sleep 10
-    - echo "No lint issues found."
-  tags:
-    - FPGA
+#lint-test-job:   # This job also runs in the test stage.
+#  stage: test    # It can run at the same time as unit-test-job (in parallel).
+#  script:
+#    - echo "Linting code... This will take about 10 seconds."
+#    - sleep 10
+#    - echo "No lint issues found."
+#  tags:
+#    - FPGA
 
-deploy-job:      # This job runs in the deploy stage.
-  stage: deploy  # It only runs when *both* jobs in the test stage complete successfully.
-  environment: production
-  script:
-    - echo "Deploying application..."
-    - echo "Application successfully deployed."
-  tags:
-    - FPGA
+#deploy-job:      # This job runs in the deploy stage.
+#  stage: deploy  # It only runs when *both* jobs in the test stage complete successfully.
+#  environment: production
+#  script:
+#    - echo "Deploying application..."
+#    - echo "Application successfully deployed."
+#  tags:
+#    - FPGA
\ No newline at end of file

set_env.sh

-#-----------------------------------------------------------------------------
-# SoC Labs Environment Setup Script
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright  2023, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-#!/bin/bash
-
-# Get Root Location of Design Structure
-if [ -z $DESIGN_ROOT ]; then
-    # If $DESIGN_ROOT hasn't been set yet
-    DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
-
-    if [ -z $DESIGN_ROOT ]; then
-        # If not in a submodule - at root
-        DESIGN_ROOT=`git rev-parse --show-toplevel`
-    fi
-
-    # Source Top-Level Sourceme
-    source $DESIGN_ROOT/set_env.sh
-else
-    # Set Environment Variable for this Repository
-    export NANOSOC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
-
-    # If this Repo is root of workspace
-    if [ $NANOSOC_DIR = $DESIGN_ROOT ]; then
-        echo "Design Workspace: $DESIGN_ROOT" 
-        export DESIGN_ROOT
-        # Set Default Simulator
-        export SIMULATOR="ivlog"
-    fi
-
-    # Source environment variables for all submodules
-    for d in $NANOSOC_DIR/* ; do
-        if [ -f "$d/.git" ]; then
-            if [ -f "$d/set_env.sh" ]; then
-            # If .git file exists - submodule
-                source $d/set_env.sh
-            fi
-        fi
-    done
-
-    # Add Scripts to Path
-    export PATH="$PATH:/$NANOSOC_DIR/flow"
-fi
\ No newline at end of file