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SoCLabs
NanoSoC Tech
Commits
b769ba02
Commit
b769ba02
authored
2 years ago
by
dam1n19
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SOC1-167
: Merge main into feature branch
parents
c04ad57b
cb75144c
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.gitlab-ci.yml
+15
-8
15 additions, 8 deletions
.gitlab-ci.yml
system/fpga_imp/CI_verification/test_bitfile_ZCU104.sh
+9
-0
9 additions, 0 deletions
system/fpga_imp/CI_verification/test_bitfile_ZCU104.sh
with
24 additions
and
8 deletions
.gitlab-ci.yml
+
15
−
8
View file @
b769ba02
...
...
@@ -17,9 +17,19 @@
# https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml
stages
:
# List of stages for jobs, and their order of execution
-
simulate
-
build
-
deploy
simulate-nanosoc
:
stage
:
simulate
script
:
-
echo "Simulation phase started"
-
sleep
5
tags
:
-
VLAB-ZCU
build-job-Z2
:
# This job runs in the build stage, which runs first.
stage
:
build
script
:
...
...
@@ -151,7 +161,7 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
# FUTURE Work: need to add error handling for if the board does not connect,
# could grep from screenlog to see if successfully connected
-
screen -r zynq -X stuff "cp -r /home/dwn1c21/FPGA/. ./ \n"
-
screen -r zynq -X stuff "./ZCU104_connect.sh \n"
-
screen -r zynq -X stuff "./ZCU104_connect.sh
> connect_log
\n"
-
sleep
10
# use scp to copy over bit files and python script
-
screen -r zynq -X stuff "scp -i ~/.ssh/id_rsa dwn1c21@soclabs.soton.ac.uk:~/builds/wzndG1mA/0/soclabs/nanosoc/system/fpga_imp/CI_verification/load_bitfile.py ./ \n"
...
...
@@ -176,13 +186,10 @@ deploy-job-ZCU104: # This job runs in the deploy stage.
-
screen -r zynq -X stuff "deactivate \n"
-
screen -r zynq -X stuff "exit \n"
# test the screenlog for "Overlay Loaded"
-
if (grep -r "Overlay Loaded" ./screenlog)
-
then
-
echo "Bit file loaded successfully"
-
else
-
echo "Bit file load failed"
-
exit
1
-
fi
-
cp ./Cortex-M0/nanosoc/systems/mcu/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./
-
chmod +x test_bitfile_ZCU104.sh
-
./test_bitfile_ZCU104.sh
after_script
:
# cleanup xilinx directories and quit screen
-
screen -r zynq -X stuff "rm load_bitfile.py \n"
...
...
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system/fpga_imp/CI_verification/test_bitfile_ZCU104.sh
0 → 100644
+
9
−
0
View file @
b769ba02
#!/bin/bash
if
(
grep
-r
"Overlay Loaded"
./screenlog
)
then
echo
"Bit file loaded successfully"
else
echo
"Bit file load failed"
exit
1
fi
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