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Commit b72b2499 authored by Daniel Newbrook's avatar Daniel Newbrook
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Restructure and update ASIC flows

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...@@ -3,7 +3,35 @@ verif/cocotb/* ...@@ -3,7 +3,35 @@ verif/cocotb/*
!verif/cocotb/makefile !verif/cocotb/makefile
!verif/cocotb/*.py !verif/cocotb/*.py
#Exclude synthesis files
ASIC/*.pvl
ASIC/*.syn
ASIC/*.mr
ASIC/*.pvk
ASIC/alib-52
ASIC/WORK/*
ASIC/Cadence/Genus/fv
ASIC/Cadence/Genus/*.rpt
ASIC/Cadence/Genus/*.tstamp
ASIC/Cadence/Innovus/.cadence
ASIC/Cadence/Innovus/nanosoc_chip_pads
ASIC/Cadence/Innovus/timingReports
ASIC/Cadence/Innovus/*.db*
ASIC/Cadence/Innovus/*.rpt
ASIC/Cadence/Innovus/*.checkFPlan
ASIC/Cadence/Innovus/*.ptiavg
ASIC/Cadence/Innovus/*.ptifiles
ASIC/Synopsys/Formality/FM_INFO/*
ASIC/Synopsys/ICC2/CLIBs
ASIC/Synopsys/ICC2/PreFrameCheck
ASIC/Synopsys/ICC2/tsmc65lp/*
ASIC/Synopsys/ICC2/*.svf
ASIC/Synopsys/ICC2/*.ems
ASIC/Synopsys/ICC2/icc2_output.txt
*.pvl
*.syn
*.mr
*.pvk
# Exclude Compiled Binaries # Exclude Compiled Binaries
/software/*/*.elf /software/*/*.elf
/software/*/*.ELF /software/*/*.ELF
......
synthesis/genus.tcl → ASIC/Cadence/Genus/genus.tcl
+ 18
− 6
View file @ b72b2499
set_db init_lib_search_path ./ set_db init_lib_search_path "$::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/ $::env(SOCLABS_PROJECT_DIR)/memories/rf/ $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/"
set BASE_LIB $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib set BASE_LIB sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib
set RF_LIB $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.lib set RF_LIB rf_sp_hdf_ss_1p08v_1p08v_125c.lib
set ROM_LIB $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.lib set ROM_LIB rom_via_ss_1p08v_1p08v_125c.lib
set_db / .library "$BASE_LIB $RF_LIB $ROM_LIB" create_library_domain domain1
set_db [get_db library_domains domain1] .library "$BASE_LIB $RF_LIB $ROM_LIB"
read_power_intent -cpf -module nanosoc_chip_pads nanosoc.cpf
source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl source $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/genus_flist.tcl
elaborate nanosoc_chip_pads elaborate nanosoc_chip_pads
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/synthesis/constraints.sdc
apply_power_intent
check_library > lib_check.log
check_cpf
commit_power_intent
check_power_structure -license lpgxl
read_sdc $::env(SOCLABS_NANOSOC_TECH_DIR)/ASIC/constraints.sdc
set_db dft_scan_style muxed_scan set_db dft_scan_style muxed_scan
define_test_signal -function test_mode TEST define_test_signal -function test_mode TEST
......
ASIC/Cadence/Genus/nanosoc.cpf 0 → 100644
+ 23
− 0
View file @ b72b2499
set_cpf_version 1.1
set_design nanosoc_chip_pads
create_power_domain -name TOP -default
create_power_domain -name ACCEL -instances u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08
create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
create_ground_nets -nets VSS
create_power_nets -nets VDD
create_power_nets -nets VDDACC
create_global_connection -net VSS -pins VSS
create_global_connection -net VDD -pins VDD
create_global_connection -net VDDACC -pins VDDACC
update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
end_design
\ No newline at end of file
synthesis/design_import.tcl → ASIC/Cadence/Innovus/design_import.tcl
+ 15
− 5
View file @ b72b2499
...@@ -6,13 +6,18 @@ ...@@ -6,13 +6,18 @@
######################################### #########################################
### Settting PG Nets ### Settting PG Nets
set_db init_power_nets {VDD VDDIO} set_db init_power_nets {VDD VDDIO VDDACC}
set_db init_ground_nets {VSS VSSIO} set_db init_ground_nets {VSS VSSIO}
### Processing MMMC ### Processing MMMC
read_mmmc nanosoc.mmmc read_mmmc nanosoc.mmmc
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc9_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc9_base_rvt/r0p0/lef/sc9_cln65lp_base_rvt.lef # Set library paths
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef
# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
...@@ -20,7 +25,7 @@ set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef ...@@ -20,7 +25,7 @@ set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef
read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${RF_LEF} ${ROM_LEF}] read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${RF_LEF} ${ROM_LEF}]
### Reading Netlist ### Reading Netlist
read_netlist ./nanosoc_chip_pads.vm read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
### Initializing the Design ### Initializing the Design
init_design init_design
...@@ -28,5 +33,10 @@ init_design ...@@ -28,5 +33,10 @@ init_design
### Adjusting the GUI ### Adjusting the GUI
gui_fit gui_fit
create_floorplan -site sc9_cln65lp -core_size 900 900 50 50 50 50 ungroup u_nanosoc_chip_u_system
create_floorplan -site sc12_cln65lp -core_size 1500 1500 50 50 50 50
read_power_intent -cpf nanosoc.cpf
synthesis/io_plan.tcl → ASIC/Cadence/Innovus/io_plan.tcl
+ 4
− 4
View file @ b72b2499
...@@ -5,12 +5,12 @@ ...@@ -5,12 +5,12 @@
############################### ###############################
### Pin Place ### Pin Place
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 30 -pin {CLK TEST NRST VDD VDDIO} edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Top -layer 9 -spread_type center -spacing 90 -pin { TEST VDD VDDIO VDDACC {P1[15]} {P1[14]} {P1[13]} {P1[12]} {P1[11]}}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 30 -pin {SWDIO SWDCK VSS VSSIO} edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Bottom -layer 9 -spread_type center -spacing 90 -pin {{P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}}
edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 30 -pin {{P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]} {P0[5]} {P0[6]} {P0[7]} {P0[8]} {P0[9]} {P0[10]} {P0[11]} {P0[12]} {P0[13]} {P0[14]} {P0[15]}} edit_pin -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Left -layer 9 -spread_type center -spacing 90 -pin {NRST CLK SWDIO SWDCK VSS VSSIO {P0[0]} {P0[1]} {P0[2]} {P0[3]} {P0[4]}}
edit_pin -pin_width 1.5 -pin_depth 1.5 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 9 -spread_type center -spacing 30 -pin {{P1[0]} {P1[1]} {P1[2]} {P1[3]} {P1[4]} {P1[5]} {P1[6]} {P1[7]} {P1[8]} {P1[9]} {P1[10]} {P1[11]} {P1[12]} {P1[13]} {P1[14]} {P1[15]}} edit_pin -pin_width 1.5 -pin_depth 1.5 -fixed_pin 1 -fix_overlap 1 -unit micron -spread_direction clockwise -side Right -layer 9 -spread_type center -spacing 90 -pin {{P1[0]} {P1[1]} {P1[2]} {P1[3]} {P1[4]} {P1[5]} {P1[6]} {P1[7]} {P1[8]} {P1[9]} {P1[10]} }
gui_fit gui_fit
ASIC/Cadence/Innovus/nanosoc.cpf 0 → 100644
+ 23
− 0
View file @ b72b2499
set_cpf_version 1.1
set_design nanosoc_chip_pads
create_power_domain -name TOP -default
create_power_domain -name ACCEL -instances u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
create_nominal_condition -name nom -voltage 1.08
create_power_mode -name PM -domain_conditions {TOP@nom ACCEL@nom} -default
create_ground_nets -nets VSS
create_power_nets -nets VDD
create_power_nets -nets VDDACC
create_global_connection -net VSS -pins VSS
create_global_connection -net VDD -pins VDD
create_global_connection -net VDDACC -pins VDDACC
update_power_domain -name TOP -primary_power_net VDD -primary_ground_net VSS
update_power_domain -name ACCEL -primary_power_net VDDACC -primary_ground_net VSS
end_design
\ No newline at end of file
synthesis/nanosoc.mmmc → ASIC/Cadence/Innovus/nanosoc.mmmc
+ 11
− 9
View file @ b72b2499
set base_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/sc9_base_rvt/r0p0 set phys_lib /research/AAA/phys_ip_library
set tech_path /home/dwn1c21/SoC-Labs/phys_ip/arm/tsmc/cln65lp/arm_tech/r2p0
set ram_path /home/dwn1c21/SoC-Labs/nanosoc_clk/accelerator-project/memories/rf/ set base_path ${phys_lib}/arm/tsmc/cln65lp/sc12_base_rvt/r0p0
set rom_path /home/dwn1c21/SoC-Labs/nanosoc_clk/accelerator-project/memories/bootrom/ set tech_path ${phys_lib}/arm/tsmc/cln65lp/arm_tech/r2p0
set ram_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/rf/
set rom_path /home/dwn1c21/SoC-Labs/accelerator-project/memories/bootrom/
create_library_set -name default_libset_max\ create_library_set -name default_libset_max\
-timing\ -timing\
[list ${base_path}/lib/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_sp_hdf_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib] \ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.lib ${ram_path}/rf_sp_hdf_ss_1p08v_1p08v_125c.lib ${rom_path}/rom_via_ss_1p08v_1p08v_125c.lib] \
-si\ -si\
[list ${base_path}/celtic/sc9_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB] [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.cdB]
create_library_set -name default_libset_min\ create_library_set -name default_libset_min\
-timing\ -timing\
[list ${base_path}/lib/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib] \ [list ${base_path}/lib/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.lib ${ram_path}/rf_sp_hdf_ff_1p32v_1p32v_m40c.lib ${rom_path}/rom_via_ff_1p32v_1p32v_m40c.lib] \
-si\ -si\
[list ${base_path}/celtic/sc9_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB] [list ${base_path}/celtic/sc12_cln65lp_base_rvt_ff_typical_min_1p32v_m40c.cdB]
create_timing_condition -name default_mapping_tc_2\ create_timing_condition -name default_mapping_tc_2\
-library_sets [list default_libset_min] -library_sets [list default_libset_min]
...@@ -67,7 +69,7 @@ create_delay_corner -name default_delay_corner_min\ ...@@ -67,7 +69,7 @@ create_delay_corner -name default_delay_corner_min\
create_constraint_mode -name default_constraint_mode\ create_constraint_mode -name default_constraint_mode\
-sdc_files\ -sdc_files\
[list ./constraints.sdc] [list ../../constraints.sdc]
create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max create_analysis_view -name default_analysis_view_setup -constraint_mode default_constraint_mode -delay_corner default_delay_corner_max
......
synthesis/place.tcl → ASIC/Cadence/Innovus/place.tcl
+ 0
− 0
View file @ b72b2499
File moved
ASIC/Cadence/Innovus/place_macros.tcl 0 → 100644
+ 25
− 0
View file @ b72b2499
#------------------------------------------------------------------------------------
# Cadence Innovus: Place macros
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# Daniel Newbrook (d.newbrook@soton.ac.uk)
# Copyright (c) 2023, SoC Labs (www.soclabs.org)
#------------------------------------------------------------------------------------
# relative floorplan
delete_relative_floorplan -all
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -30 1} -vertical_edge_separate {2 -20 2} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -30 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type object -horizontal_edge_separate {3 -30 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type object -orient R0 -horizontal_edge_separate {3 -30 1} -vertical_edge_separate {3 0 3} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf -ref u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf
create_relative_floorplan -ref_type core_boundary -orient R180 -horizontal_edge_separate {3 20 3} -vertical_edge_separate {2 -40 2} -place u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
create_relative_floorplan -ref_type core_boundary -horizontal_edge_separate {1 -500 1} -vertical_edge_separate {0 50 0} -place u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator
create_partition -hinst u_nanosoc_chip_u_system_u_ss_expansion_u_region_exp_u_ss_accelerator -core_spacing 0.0 0.0 0.0 0.0 -rail_width 0.0 -min_pitch_left 2 -min_pitch_right 2 -min_pitch_top 2 -min_pitch_bottom 2 -reserved_layer { 1 2 3 4 5 6 7 8 9 10} -pin_layer_top { 2 4 6 8 10} -pin_layer_left { 3 5 7 9} -pin_layer_bottom { 2 4 6 8 10} -pin_layer_right { 3 5 7 9} -place_halo 0.1 0.1 0.1 0.1 -route_halo 0.0 -route_halo_top_layer 10 -route_halo_bottom_layer 1
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_l_u_expram_l_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_expansion_u_region_expram_h_u_expram_h_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_imem_0_u_imem_0_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_dmem_0_u_dmem_0_u_sram_u_rf_sp_hdf
create_place_halo -halo_deltas {5 5 5 5} -insts u_nanosoc_chip_u_system_u_ss_cpu_u_region_bootrom_0_u_bootrom_cpu_0_u_bootrom_u_sl_rom
\ No newline at end of file
synthesis/pnr_flow.tcl → ASIC/Cadence/Innovus/pnr_flow.tcl
+ 5
− 0
View file @ b72b2499
...@@ -14,6 +14,11 @@ source design_import.tcl ...@@ -14,6 +14,11 @@ source design_import.tcl
### IO Planning ### IO Planning
source io_plan.tcl source io_plan.tcl
### Memory and accelerator placement
source place_macros.tcl
commit_power_intent
check_power_domains
### Power Plan ### Power Plan
source power_plan.tcl source power_plan.tcl
......
ASIC/Cadence/Innovus/power_plan.tcl 0 → 100644
+ 42
− 0
View file @ b72b2499
#########################################
# Script : Power Planning
# Tool : Cadence Innovus
# Date : May 22, 2023
# Author : Srimanth Tenneti
#########################################
### Connecting Global Nets
connect_global_net VDD -type pg_pin -pin_base_name VDD -inst_base_name *
connect_global_net VDDACC -type pg_pin -pin_base_name VDDACC -inst_base_name *
connect_global_net VDDIO -type pg_pin -pin_base_name VDDIO -inst_base_name *
connect_global_net VSS -type pg_pin -pin_base_name VSS -inst_base_name *
connect_global_net VSSIO -type pg_pin -pin_base_name VSSIO -inst_base_name *
### Top and Bottom Metal Declartions
set_db add_rings_stacked_via_top_layer M8
set_db add_rings_stacked_via_bottom_layer M1
### Adding Rings
add_rings -nets {VDD VDDACC VDDIO VSS VSSIO} -type core_rings -follow core -layer {top M7 bottom M7 left M8 right M8} -width {top 8 bottom 8 left 8 right 8} -spacing {top 2 bottom 2 left 2 right 2} -offset {top 1 bottom 1 left 1 right 1} -center 0 -threshold 0 -jog_distance 0 -snap_wire_center_to_grid none
### Adding Stripes
set_db add_stripes_ignore_block_check true
set_db add_stripes_break_at none
set_db add_stripes_route_over_rows_only false
set_db add_stripes_rows_without_stripes_only false
set_db add_stripes_extend_to_closest_target none
set_db add_stripes_stop_at_last_wire_for_area false
set_db add_stripes_partial_set_through_domain true
set_db add_stripes_ignore_non_default_domains false
set_db add_stripes_trim_antenna_back_to_shape none
set_db add_stripes_spacing_type edge_to_edge
set_db add_stripes_spacing_from_block 0
set_db add_stripes_stripe_min_length stripe_width
set_db add_stripes_stacked_via_top_layer AP
set_db add_stripes_stacked_via_bottom_layer M1
set_db add_stripes_via_using_exact_crossover_size false
set_db add_stripes_split_vias false
set_db add_stripes_orthogonal_only true
set_db add_stripes_allow_jog { padcore_ring block_ring }
set_db add_stripes_skip_via_on_pin { standardcell }
set_db add_stripes_skip_via_on_wire_shape { noshape }
add_stripes -nets {VDD VDDACC VSS} -layer M8 -direction vertical -width 4 -spacing 1.8 -number_of_sets 8 -extend_to last_padring -start_from left -start_offset 100 -stop_offset 100 -switch_layer_over_obs false -max_same_layer_jog_length 2 -pad_core_ring_top_layer_limit AP -pad_core_ring_bottom_layer_limit M1 -block_ring_top_layer_limit AP -block_ring_bottom_layer_limit M1 -use_wire_group 0 -snap_wire_center_to_grid none
ASIC/Cadence/Innovus/power_route.tcl 0 → 100644
+ 10
− 0
View file @ b72b2499
##################################
# Script : Special Route Script
# Date : May 24, 2023
# Description : Power Routing
# Author : Srimanth Tenneti
##################################
route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { ACCEL } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDDACC VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
route_special -connect {block_pin pad_pin pad_ring core_pin floating_stripe} -layer_change_range { M1(1) AP(10) } -block_pin_target nearest_target -pad_pin_port_connect {all_port one_geom} -pad_pin_target nearest_target -core_pin_target first_after_row_end -floating_stripe_target {block_ring pad_ring ring stripe ring_pin block_pin followpin} -allow_jogging 1 -power_domains { TOP } -crossover_via_layer_range { M1(1) AP(10) } -nets { VDD VSS } -allow_layer_change 1 -block_pin use_lef -target_via_layer_range { M1(1) AP(10) }
#route_special -nets {VDD VSS} -connect core_pin -block_pin_target nearest_target -core_pin_target first_after_row_end -allow_jogging 1 -allow_layer_change 1 -layer_change_range { M1(1) M8(8) } -crossover_via_layer_range { M1(1) M8(8) } -target_via_layer_range { M1(1) M8(8) }
synthesis/route.tcl → ASIC/Cadence/Innovus/route.tcl
+ 0
− 0
View file @ b72b2499
File moved
synthesis/synopsys.tcl → ASIC/Synopsys/DC/synopsys.tcl
+ 119
− 0
View file @ b72b2499
...@@ -44,25 +44,76 @@ current_design $top_module ...@@ -44,25 +44,76 @@ current_design $top_module
# Link Design # Link Design
link link
read_sdc constraints.sdc read_sdc ../../constraints.sdc
create_power_domain pd_top -include_scope
add_port_state VSS -state {state1 0.00} add_port_state VSS -state {state1 0.00}
add_port_state VDD -state {state1 1.08} add_port_state VDD -state {state1 1.08}
add_port_state VSSACC -state {state1 0.00}
add_port_state VDDACC -state {state1 1.08}
add_port_state VSSIO -state {state1 0.00} add_port_state VSSIO -state {state1 0.00}
add_port_state VDDIO -state {state1 3.3} add_port_state VDDIO -state {state1 3.3}
connect_supply_net pd_top.primary.power -port VDD # Visual UPF added these lines...
connect_supply_net pd_top.primary.ground -port VSS #Scope: nanosoc_chip_pads
create_supply_set SSET1
create_supply_set SSET2
#Domain: ACCEL
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
set_domain_supply_net ACCEL -primary_power_net SSET2.power -primary_ground_net SSET2.ground
#Domain: MEM
create_power_domain MEM -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram}
set_domain_supply_net MEM -primary_power_net SSET1.power -primary_ground_net SSET1.ground
#Domain: TOP
create_power_domain TOP
set_domain_supply_net TOP -primary_power_net SSET1.power -primary_ground_net SSET1.ground
add_power_state SSET1 -state state1 { -supply_expr {power == `{FULL_ON, 1.080000}}}
add_power_state SSET1 -state state2 { -supply_expr {ground == `{FULL_ON, 0.000000}}}
add_power_state SSET2 -state state3 { -supply_expr {power == `{FULL_ON, 1.080000}}}
add_power_state SSET2 -state state4 { -supply_expr {ground == `{FULL_ON, 0.000000}}}
connect_supply_net SSET1.power -port VDD
connect_supply_net SSET1.ground -port VSS
connect_supply_net SSET2.power -port VDDACC
connect_supply_net SSET2.ground -port VSSACC
set_voltage -object_list {SSET1.power SSET2.power MEM.primary.power TOP.primary.power ACCEL.primary.power} 1.08
set_voltage -object_list {SSET1.ground SSET2.ground MEM.primary.ground TOP.primary.ground ACCEL.primary.ground} 0.00
compile_ultra -exact_map connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VDD
connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VDD
connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VDD
connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VDD
connect_supply_net MEM.primary.power -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VDDE
connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf/VSS
connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf/VSS
connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf/VSS
connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf/VSS
connect_supply_net MEM.primary.ground -ports u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom/VSSE
set_app_var compile_delete_unloaded_sequential_cells false
compile_ultra -gate_clock -scan
set_scan_configuration -chain_count 1
create_test_protocol -infer_clock -infer_asynch
dft_drc
insert_dft
write -hierarchy -format verilog -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
write_scan_def -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
write_test_protocol -output $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads_scan.stil
write -hierarchy -format verilog -output ./nanosoc_chip_pads.vm
redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area } redirect [format "%s%s%s" $report_path $top_module _area.rep] { report_area }
redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference } redirect -append [format "%s%s%s" $report_path $top_module _area.rep] { report_reference }
redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power } redirect [format "%s%s%s" $report_path $top_module _power.rep] { report_power }
redirect [format "%s%s%s" $report_path $top_module _scan_path.rep] { report_scan_path }
redirect [format "%s%s%s" $report_path $top_module _timing.rep] \ redirect [format "%s%s%s" $report_path $top_module _timing.rep] \
{ report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit} { report_timing -path full -max_paths 100 -nets -transition_time -capacitance -significant_digits 3 -nosplit}
ASIC/Synopsys/Formality/fm_shell.tcl 0 → 100644
+ 25
− 0
View file @ b72b2499
set_mismatch_message_filter -warn FMR_ELAB-147
set_svf -append $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/default.svf
source $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/flist/formality_flist.tcl
read_db -r $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
read_db -r $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
set_top nanosoc_chip_pads
# Read db files
read_db -i $env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/db/sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c.db
read_db -i $env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf_ss_1p08v_1p08v_125c.db
read_db -i $env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via_ss_1p08v_1p08v_125c.db
# Read Gate netlist
read_verilog -i $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm
set_top nanosoc_chip_pads
match
verify
analyze_points -failing
save_session nanosoc_chip_pads_formal_equivalence
\ No newline at end of file
ASIC/Synopsys/ICC2/place_memories.tcl 0 → 100644
+ 16
− 0
View file @ b72b2499
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.47} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.67} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.05} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf}] -target_orientation R0 -target_corner tr -anchor_corner tr -offset {-0.1 -0.27} -offset_type scalable
set_macro_relative_location -target_object [get_cell {u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom}] -target_orientation R180 -target_corner br -anchor_corner br -offset {-0.15 0.1} -offset_type scalable
create_macro_relative_location_placement
set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram/u_rf_sp_hdf] -name physical_status -value fixed
set_attribute -objects [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] -name physical_status -value fixed
create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram/u_rf_sp_hdf] ref_block];
create_keepout_margin -type hard -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type hard_macro -outer {5 5 5 5} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];create_keepout_margin -type soft -outer {8 8 8 8} [get_attribute [get_cells u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom/u_sl_rom] ref_block];
synthesis/ICC2/place_pins.tcl → ASIC/Synopsys/ICC2/place_pins.tcl
+ 1
− 1
View file @ b72b2499
set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1 set_individual_pin_constraints -ports {P0[15] P0[14] P0[13] P0[12] P0[11] P0[10] P0[9] P0[8] P0[7] P0[6] P0[5] P0[4] P0[3] P0[2] P0[1] P0[0]} -sides 1
set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3 set_individual_pin_constraints -ports {P1[15] P1[14] P1[13] P1[12] P1[11] P1[10] P1[9] P1[8] P1[7] P1[6] P1[5] P1[4] P1[3] P1[2] P1[1] P1[0]} -sides 3
set_individual_pin_constraints -ports {CLK TEST VDD VDDIO} -sides 2 set_individual_pin_constraints -ports {CLK TEST VDD VDDIO VDDACC} -sides 2
set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4 set_individual_pin_constraints -ports {NRST VSS VSSIO SWDIO SWDCK} -sides 4
place_pins -self place_pins -self
\ No newline at end of file
synthesis/ICC2/icc_shell.tcl → ASIC/Synopsys/ICC2/pnr.tcl
+ 68
− 14
View file @ b72b2499
...@@ -22,17 +22,53 @@ read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2 ...@@ -22,17 +22,53 @@ read_parasitic_tech -name rcbest -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2
read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map read_parasitic_tech -name rcworst -tlup $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/rcworst.tluplus -layermap $PHYS_IP_DIR/arm/tsmc/cln65lp/arm_tech/r2p0/synopsys_tluplus/1p9m_6x2z/tluplus.map
read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm read_verilog -library tsmc65lp -design nanosoc_chip_pads -top nanosoc_chip_pads $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.vm
read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.def read_def $env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/Synopsys/nanosoc_chip_pads.def
link_block link_block
initialize_floorplan -control_type die -keep_pg_route -core_utilization 0.55 -macro_utilization 0.2 -side_ratio {1 1} -core_offset {100 100} -keep_placement {all} initialize_floorplan -side_length {1600 1600} -core_offset {100}
create_io_ring -name main_io create_io_ring -name main_io
explore_logic_hierarchy -organize explore_logic_hierarchy -organize
load_upf ../nanosoc_chip_pads_power.upf # Place IO pins
commit_upf source place_pins.tcl
# Power domains TOP ACCEL and MEM
create_power_domain TOP
create_power_domain ACCEL -elements {u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator}
create_power_domain MEM -elements {u_nanosoc_chip/u_system/u_ss_cpu/u_region_dmem_0/u_dmem_0/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_bootrom_0/u_bootrom_cpu_0/u_bootrom u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_l/u_expram_l/u_sram u_nanosoc_chip/u_system/u_ss_expansion/u_region_expram_h/u_expram_h/u_sram u_nanosoc_chip/u_system/u_ss_cpu/u_region_imem_0/u_imem_0/u_sram}
#VDD
create_supply_port VDD
create_supply_net VDD -domain TOP
create_supply_net VDD -domain MEM -reuse
connect_supply_net VDD -ports VDD
#VSS
create_supply_port VSS
create_supply_net VSS -domain TOP
create_supply_net VSS -domain MEM -reuse
create_supply_net VSS -domain ACCEL -reuse
connect_supply_net VSS -ports VSS
#VDDACC
create_supply_port VDDACC
create_supply_net VDDACC -domain ACCEL
connect_supply_net VDDACC -ports VDDACC
#IO Supplies
create_supply_port VDDIO -domain TOP
connect_supply_net VDDIO -ports VDDIO
set_domain_supply_net TOP -primary_power_net VDD -primary_ground_net VSS
set_domain_supply_net ACCEL -primary_power_net VDDACC -primary_ground_net VSS
set_domain_supply_net MEM -primary_power_net VDD -primary_ground_net VSS
# Create voltage and power region for accelerator
create_voltage_area -power_domains ACCEL -power VDDACC -ground VSS -nwell VDDACC -pwell VSS -region {{{150 1050} {1100 1650}}} -name VA_ACCEL -cells [get_cells -physical_context -hierarchical \
-regexp u_nanosoc_chip/u_system/u_ss_expansion/u_region_exp/u_ss_accelerator/.*]
create_pg_region {pg_ACCEL} -voltage_area VA_ACCEL -expand {0 10}
set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125 set_parasitic_parameters -early_spec rcbest -early_temperature -40 -late_spec rcworst -late_temperature 125
current_corner default current_corner default
...@@ -43,37 +79,55 @@ current_corner default ...@@ -43,37 +79,55 @@ current_corner default
set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c set_operating_conditions -max_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -max ss_typical_max_1p08v_125c -min_library sc12_cln65lp_base_rvt_ss_typical_max_1p08v_125c -min ss_typical_max_1p08v_125c
current_mode default current_mode default
set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD] set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDD]
set_voltage 1.08 -corner [current_corner] -object_list [get_supply_nets VDDACC]
set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO] set_voltage 3.00 -corner [current_corner] -object_list [get_supply_nets VDDIO]
set_voltage 0.00 -corner [current_corner] -object_list [get_supply_nets VSS]
add_port_state VSS -state {on 0.0}
add_port_state VDD -state {on 1.08}
add_port_state VDDACC -state {on 1.08}
add_port_state VDDIO -state {on 3.0}
create_pst ao_pst -supplies {VSS VDD VDDACC VDDIO}
add_pst_state ao -pst ao_pst -state {on on on on}
set_voltage_area -add_power_domains MEM DEFAULT_VA
commit_upf
set_app_options -list {opt.timing.effort {medium}} set_app_options -list {opt.timing.effort {medium}}
set_app_options -list {clock_opt.place.effort {high}} set_app_options -list {clock_opt.place.effort {high}}
set_app_options -list {place_opt.flow.clock_aware_placement {true}} set_app_options -list {place_opt.flow.clock_aware_placement {true}}
set_app_options -list {place_opt.final_place.effort {high}} set_app_options -list {place_opt.final_place.effort {high}}
set_app_options -list {clock_opt.hold.effort {ultra}}
read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/synthesis/constraints.sdc read_sdc $env(SOCLABS_PROJECT_DIR)/nanosoc_tech/ASIC/constraints.sdc
update_timing update_timing
change_selection [explore_logic_hierarchy -create_module_boundary]
explore_logic_hierarchy -place -rectangular
# Place IO pins
source place_pins.tcl change_selection [explore_logic_hierarchy -create_module_boundary]
explore_logic_hierarchy -place
#Place and fix memories with boundary #Place and fix memories with boundary
source place_memories.tcl source place_memories.tcl
change_selection [explore_logic_hierarchy -create_module_boundary]
explore_logic_hierarchy -place
#Create power ring and straps #Create power ring and straps
source power_plan.tcl source power_plan.tcl
#Start Placement #Start Placement
create_placement create_placement
legalize_placement -cells [get_cells -design [current_block]] legalize_placement -cells [get_cells *]
save_lib -all save_lib -all
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/1pre_opt_placement_timing.rep
check_mv_design > check_mv_design.log
report_utilization -of_objects [get_voltage_areas {DEFAULT_VA}] > check_util_default_va.log
report_utilization -of_objects [get_voltage_areas {VA_ACCEL}] > check_util_va_accel.log
place_opt place_opt
save_lib -all save_lib -all
...@@ -95,4 +149,4 @@ update_timing -full ...@@ -95,4 +149,4 @@ update_timing -full
report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_timing.rep report_timing > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_timing.rep
report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_power.rep report_power > $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/reports/final_power.rep
save_lib -all save_lib -all
exit exit
\ No newline at end of file
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