Update nanosoc_tb_qs.v

verif/tb/verilog/nanosoc_tb_qs.v

@@ -289,9 +289,16 @@ reg baud_clk_del;
   wire rxd8_tvalid;
   wire [7:0] rxd8_tdata ;
 
+`ifdef FAST_SIM
+  parameter FAST_LOAD = 1;
+`else
+  parameter FAST_LOAD = 0;
+`endif
+
 `ifndef COCOTB_SIM
   nanosoc_axi_stream_io_8_txd_from_file #(
-    .TXDFILENAME(ADP_FILENAME)
+    .TXDFILENAME(ADP_FILENAME),
+    .FAST_LOAD(FAST_LOAD)
   ) u_nanosoc_axi_stream_io_8_txd_from_file (
     .aclk       (CLK),
     .aresetn    (NRST),