SOC1-230: Started building DMA Subsystem

.gitmodules

@@ -4,3 +4,6 @@
 [submodule "system/slcore_m0_tech"]
 	path = system/slcore_m0_tech
 	url = https://git.soton.ac.uk/soclabs/slcore_m0_tech.git
+[submodule "system/sldma230_tech"]
+	path = system/sldma230_tech
+	url = https://git.soton.ac.uk/soclabs/sldma230_tech.git

system/nanosoc_subsystems/dma/verilog/nanosoc_ss_dma.v

+//-----------------------------------------------------------------------------
+// NanoSoC DMA Subsystem - Contains DMA Controllers
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module nanosoc_ss_dma #(
+    parameter    SYS_ADDR_W        = 32,  // System Address Width
+    parameter    SYS_DATA_W        = 32,  // System Data Width
+    parameter    DMA_0_CFG_ADDR_W  = 12,  // DMAC 0 Configuration Port Address Width
+    parameter    DMA_1_CFG_ADDR_W  = 0,   // DMAC 1 Configuration Port Address Width
+    parameter    DMA_0_CHANNEL_NUM = 2,   // DMAC 0 Number of DMA Channels 
+    parameter    DMA_1_CHANNEL_NUM = 0    // DMAC 1 Number of DMA Channels
+)(
+    // AHB Clocks and Resets 
+    input wire                           SYS_HCLK,
+    input wire                           SYS_HRESETn,
+
+    // AHB Lite Port
+    output wire         [SYS_ADDR_W-1:0] DMA_0_HADDR,       // Address bus
+    output wire                    [1:0] DMA_0_HTRANS,      // Transfer type
+    output wire                          DMA_0_HWRITE,      // Transfer direction
+    output wire                    [2:0] DMA_0_HSIZE,       // Transfer size
+    output wire                    [2:0] DMA_0_HBURST,      // Burst type
+    output wire                    [3:0] DMA_0_HPROT,       // Protection control
+    output wire         [SYS_DATA_W-1:0] DMA_0_HWDATA,      // Write data
+    output wire                          DMA_0_HMASTLOCK,   // Locked Sequence
+    input  wire         [SYS_DATA_W-1:0] DMA_0_HRDATA,      // Read data bus
+    input  wire                          DMA_0_HREADY,      // HREADY feedback
+    input  wire                          DMA_0_HRESP,       // Transfer response
+    
+    // APB Configurtation Port
+    input  wire                          DMA_0_PCLKEN,      // APB clock enable
+    input  wire                          DMA_0_PSEL,        // APB peripheral select
+    input  wire                          DMA_0_PEN,         // APB transfer enable
+    input  wire                          DMA_0_PWRITE,      // APB transfer direction
+    input  wire   [DMA_0_CFG_ADDR_W-1:0] DMA_0_PADDR,       // APB address
+    input  wire         [SYS_DATA_W-1:0] DMA_0_PWDATA,      // APB write data
+    output wire         [SYS_DATA_W-1:0] DMA_0_PRDATA,      // APB read data
+    
+    // DMA Request and Status Port
+    input  wire  [DMA_0_CHANNEL_NUM-1:0] DMA_0_DMA_REQ,     // DMA transfer request
+    output wire  [DMA_0_CHANNEL_NUM-1:0] DMA_0_DMA_DONE,    // DMA transfer done
+    output wire                          DMA_0_DMA_ERR      // DMA slave response not OK
+);
+
+endmodule
\ No newline at end of file

sldma230_tech @ 858deb1b

+Subproject commit 858deb1bd8a17fafabf015d702c5891236d024fb