test/diagnostic pad configuration prototype added

nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v

@@ -65,7 +65,7 @@ module nanosoc_chip #(
   // Scan Wiring
   wire                     SYS_SCANENABLE;      // Scan Mode Enable
   wire                     SYS_TESTMODE;        // Test Mode Enable (Override Synchronisers)
-  wire                     SYS_SCANINHCLK;      // HCLK scan wire
+  wire                     SYS_SCANINHCLK;      // HCLK scan wire - TIE OFF
   wire                     SYS_SCANOUTHCLK;     // Scan Chain Output - UNUSED
   
   // Serial-Wire Debug

verif/tb/verilog/nanosoc_tb.v

@@ -41,8 +41,11 @@
 module nanosoc_tb;
 
   wire        CLK;   // crystal pin 1
-  wire        TEST;   // crystal pin 2
+  wire        TEST;  // 0 for system usaged
   wire        NRST;    // active low reset
+  wire        NRST_early;  // active low reset
+  wire        NRST_late;   // active low reset
+  wire        NRST_ext;    // active low reset
 
   wire [15:0] P0;      // Port 0
   wire [15:0] P1;      // Port 1
@@ -130,13 +133,13 @@ SROM_Ax32
   nanosoc_clkreset u_nanosoc_clkreset(
   .CLK       (CLK),
   .NRST      (NRST),
-  .NRST_early( ),
-  .NRST_late ( ),
-  .NRST_ext  ( )
+  .NRST_early(NRST_early),
+  .NRST_late (NRST_late),
+  .NRST_ext  (NRST_ext )
   );
   `endif
 
-  assign TEST=1'b0;
+  assign TEST = 1'b0;
   
   // Pullup to suppress X-inputs
   pullup(P0[ 0]);
@@ -173,6 +176,7 @@ SROM_Ax32
   pullup(P1[14]);
   pullup(P1[15]);
 
+
  // --------------------------------------------------------------------------------
  // UART output capture
  // --------------------------------------------------------------------------------

verif/tb/verilog/nanosoc_tb_qs.v

@@ -40,7 +40,7 @@
 module nanosoc_tb_qs;
 
   wire        CLK;   // crystal pin 1
-  wire        TEST = 1'b0;   // crystal pin 2
+  wire        TEST;  // 0 for system usage
   wire        NRST;    // active low reset
 
   wire [15:0] P0;      // Port 0
@@ -135,6 +135,8 @@ SROM_Ax32
   );
   `endif
 
+  assign TEST = 1'b0;
+
   // Pullup to suppress X-inputs
   pullup(P0[ 0]);
   pullup(P0[ 1]);