Updated makeflow for defines genration

fpga/makefile

@@ -39,6 +39,10 @@ IMP_NANOSOC_DIR      := $(IMPLEMENTATION_DIR)/nanosoc
 IMP_SOCKET_DIR       := $(IMPLEMENTATION_DIR)/socket
 PROJECT_DIR          := $(IMPLEMENTATION_DIR)/targets/$(BOARD_NAME)
 
+# Location of Defines File
+DEFINES_DIR          := $(SOCLABS_PROJECT_DIR)/system/src/defines/
+DEFINES_FILE         := $(DEFINES_DIR)/gen_defines.v
+
 # Name of generated filelist by python script
 TCL_FLIST_DIR        := $(IMP_NANOSOC_DIR)/flist
 TCL_OUTPUT_FILELIST  := $(TCL_FLIST_DIR)/gen_flist.tcl
@@ -65,21 +69,24 @@ endif
 ACCELERATOR ?= yes
 
 ifeq ($(ACCELERATOR),yes)
-	ACCELERATOR_SUBSYSTEM = 1
+	ACCELERATOR_SUBSYSTEM = ACCELERATOR_SUBSYSTEM
 else
 	ACCELERATOR_SUBSYSTEM = 0
 endif
 
 # Defines to pass to filelist compile
-NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM=$(ACCELERATOR_SUBSYSTEM)
+NANOSOC_DEFINES += $(ACCELERATOR_SUBSYSTEM)
 
 # Compile Testcodes and Bootrom
 code:
 	@echo Compiling Firmware
-	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) compile_all_code
+	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) bootrom
+
+defs_nanosoc:
+	@$(MAKE) -C $(SOCLABS_NANOSOC_TECH_DIR) defs_gen DEFINES_DIR=$(DEFINES_DIR) NANOSOC_DEFINES=$(NANOSOC_DEFINES) DEFINES_FILE=$(DEFINES_FILE)
 
 # Generate TCL filelist from flists
-flist_nanosoc:
+flist_nanosoc: defs_nanosoc
 	@mkdir -p $(TCL_FLIST_DIR)
 	@(cd $(TCL_FLIST_DIR); \
 	$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/filelist_compile.py -t -f $(DESIGN_VC) -o $(TCL_OUTPUT_FILELIST) -r $(IMP_NANOSOC_DIR) -d $(NANOSOC_DEFINES);)

makefile

@@ -92,6 +92,7 @@ ACCELERATOR ?= yes
 
 ifeq ($(ACCELERATOR),yes)
 	DEFINES_VC += +define+ACCELERATOR_SUBSYSTEM
+	NANOSOC_DEFINES += ACCELERATOR_SUBSYSTEM
 endif
 
 # Is the Arm QuickStart being used?
@@ -157,6 +158,10 @@ HAL_WAIVE += -design_info $(LINT_INFO_SLCOREM0_DIR)/slcorem0_ip.waive
 HAL_WAIVE += -design_info $(LINT_INFO_SLDMA230_DIR)/sldma230_ip.waive 
 HAL_WAIVE += -design_info $(LINT_INFO_SOCDEBUG_DIR)/socdebug_controller_ip.waive
 
+# Location of Defines File
+DEFINES_DIR          := $(SOCLABS_PROJECT_DIR)/system/src/defines/
+DEFINES_FILE         := $(DEFINES_DIR)/gen_defines.v
+
 # Debug Tester image
 DEBUGTESTER  = debugtester
 
@@ -243,7 +248,7 @@ all     : all_$(SIMULATOR)
 # ------- VCS -----------
 
 # Compile RTL
-compile_vcs :
+compile_vcs : defs_gen
 	vcs $(VCS_OPTIONS) $(VCS_VC_OPTIONS) $(DEFINES_VC)  | tee compile_vcs.log
 
 
@@ -263,14 +268,14 @@ sim_vcs : code
 
 	
 # Compile RTL
-compile_xm : bootrom
+compile_xm : bootrom defs_gen
 	@echo ADP_FILE
 	@echo $(ADP_OPTIONS)
 	cd $(SIM_DIR); xmprep  +overwrite $(XM_VC_OPTIONS) $(DEFINES_VC) +debug -timescale 1ns/1ps -top $(TB_TOP) | tee compile_xm.log
 	cd $(SIM_DIR); xmvlog  -work worklib -f xmvlog_ver.args | tee -a compile_xm.log
 	cd $(SIM_DIR); xmelab  -mess -f xmelab.args -access +r | tee -a compile_xm.log
 
-lint_xm: bootrom
+lint_xm: bootrom defs_gen
 	@rm -rf $(LINT_DIR) 
 	@mkdir -p $(LINT_DIR)
 	cd $(LINT_DIR); xrun -hal -f $(DESIGN_VC) $(DEFINES_VC) +debug "-timescale 1ns/1ps" -top $(LINT_TOP) $(HAL_BLACK_BOX) $(HAL_WAIVE) $(LINT_NOCHECK)
@@ -296,7 +301,7 @@ sim_xm : code compile_xm
 # ------- MTI -----------
 
 # Compile RTL
-compile_mti : bootrom
+compile_mti : bootrom defs_gen
 	@echo ADP_FILE
 	@echo $(ADP_OPTIONS)
 	cd $(SIM_DIR)
@@ -354,6 +359,9 @@ regression_$(SIMULATOR): compile_$(SIMULATOR) bootrom debugtester
 	@make -j$(PARALLEL_TESTS) all_$(SIMULATOR) REGRESSION=$(REGRESSION_DIR)
 	@make -j1 regression_results REGRESSION=$(REGRESSION_DIR)
 	
+defs_gen:
+	@mkdir -p $(DEFINES_DIR)
+	@$(SOCLABS_SOCTOOLS_FLOW_DIR)/bin/defines_compile.py -d $(NANOSOC_DEFINES) -o $(DEFINES_FILE)
 	
 # ------- Software -----------
 

nanosoc/nanosoc_chip/chip/verilog/nanosoc_chip.v

+//-----------------------------------------------------------------------------
+// Nanosoc Chip-level File
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+`include "gen_defines.v"
+
 module nanosoc_chip #(
   parameter integer FT1248_WIDTH	  = 1 // FTDI Interface 1,2,4 width supported
 )(

socdebug_tech @ e798f861

-Subproject commit 46ee61270c6bb8a9723da36645ed4a76ff744ad1
+Subproject commit e798f8612a9a66322b80cb8ee8fb2606e7e9794b