update QS testbench for 38K4 uart tests

verif/tb/verilog/nanosoc_tb_qs.v

@@ -184,24 +184,36 @@ SROM_Ax32
 
  // --------------------------------------------------------------------------------
  // external UART phase lock to (known) baud rate
+ // --------------------------------------------------------------------------------
+ // UART output capture
+ // --------------------------------------------------------------------------------
+`ifdef ARM_CMSDK_SLOWSPEED_PCLK
+  // If PCLK is running at slower speed, the UART output will also be slower
+  assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
+`else
+  assign PCLK = CLK;
+`endif
+
+ // --------------------------------------------------------------------------------
+ // external UART phase lock to (known) baud rate
 
 // seem unable to use the following (due to generate instance naming?)
 //  wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
 
-// 2000000/208 = 9615 baud (+0.16%)
-// 208 / 16
-`define BAUDPROG 130
+// 240000000/6250 = 38400 baud
+// 6250/16 = 390.625
+`define BAUDPROGDIV16 389
 
- reg [7:0] bauddiv;
- wire    baudclken = (bauddiv == 8'b00000000);
+ reg [8:0] bauddiv;
+ wire    baudclken = (bauddiv == 9'b0);
 
   always @(negedge NRST or posedge PCLK)
     if (!NRST)
       bauddiv <=0;
     else
-      bauddiv <= (baudclken) ? (`BAUDPROG-1) : (bauddiv -1) ;   // count down of BAUDPROG
+      bauddiv <= (baudclken) ? (`BAUDPROGDIV16-1) : (bauddiv -1) ;   // count down of BAUDPROG
 
-  wire baudx16_clk = bauddiv[7]; //prefer:// !baudclken;
+  wire baudx16_clk = bauddiv[8]; //prefer:// !baudclken;
 
   wire UARTXD =  P1[5];
   reg  UARTXD_del;
@@ -232,6 +244,7 @@ reg baud_clk_del;
     else
       baud_clk_del <= baud_clk;
 
+
  // --------------------------------------------------------------------------------
  // set FASTMODE true if UART simulation mode is programmed
   wire FASTMODE = 1'b0;